Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability

1. Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability Pascal BENOIT G. Sassatelli – L. Torres – D. Demigny M. Robert – G. Cambon Name.Surname@lirmm.fr

2. Outline • Context • Remanence • Operative Density • Case Study: the Systolic Ring • Conclusion and perspectives

3. Context • SoC and Customizable Platform Based-Design DSP Reconfigurable Hardware (Fine Grain) Specifications Processing power Area Power consumption etc. ASIC 2 Reconfigurable Hardware (Coarse Grain) ASIC 1 We need metrics to compare !

4. Context • Architecture characterization • Processing power • Power consumption • Flexibility • Parallelism potential • Dynamism • Silicon area • Scalability • … • Metrics • Dehon criterion • Remanence • Operative density Generalisation to Architectural model characterisation and metrics depend on architectural parameters « Comparing architectures with a minimum of criteria »

5. Remanence Fc • Definition NPE: # of processing elements (PE) Nc: # of PE configurable per cycle Fe: operating frequency Fc configuration frequency • Characterizes the Dynamism • # of cycles to (re)configure the whole architecture • Amount of data to compute between 2 configurations Fe

6. Remanence • Comparisons • Only 1 cycle to (re)configure the DSP • Few cycles to (re)configure coarse grain RA (8) • Many cycles to (re)configure fine grain RA Name Type NPE Nc F (MHz) R ARDOISE Fine Grain RA 2304 0.14 33 16457 MorphoSys Coarse Grain RA 128 16 100 8 Systolic Ring Coarse Grain RA 24 4 200 6 DART Coarse Grain RA 24 4 130 6 TMS320C62 DSP VLIW 8 8 300 1

7. Operative Density • Definition • NPE: # of PE A: Core Area (relative unit ²) • Area can be expressed as a function of NPE (architectural model) • Characterizes • Fixed NPE • # of operators per relative area unit • Variable NPE • OD as a function of NPE • A(NPE) = NPE*APE+Ainterconnect(NPE)+Amemory(NPE)Asequencer(NPE) • OD(NPE) = k  A(NPE) =k.NPE the architectural model is scalable

8. Operative Density • Comparisons • DSP: sequencer area • ARDOISE : fine granularity • Coarse granularity • Reconfigurable architectures • Scalabilty of interconnect resources ? • Generalization to architectural models l l Name Name Type Type Area(M Area(M ² ² ) ) NPE OD (NPE) ARDOISE ARDOISE 0.2 0.2 Fine Grain RA Fine Grain RA 26 26 12300 12300 Systolic Ring (S=1, C=6, N=2) Systolic Ring (S=1, C=6, N=2) 4.8 4.8 Coarse Grain RA Coarse Grain RA 24 24 500 500 DART DART 8.0 8.0 Coarse Grain RA Coarse Grain RA 24 24 300 300 Systolic Ring (S=1, C=16, N=4) Systolic Ring (S=1, C=16, N=4) 1.7 1.7 Coarse Grain RA Coarse Grain RA 128 128 7600 7600 MorphoSys MorphoSys 2.3 2.3 Coarse Grain RA Coarse Grain RA 128 128 5500 5500 TMS320C62 TMS320C62 0.1 0.1 DSP VLIW DSP VLIW 8 8 12300 12300

9. Architectural Model Characterization - A Case Study: • The Systolic Ring

10. Architectural model Characterization • The Systolic Ring Architectural model • Based on a coarse-grained configurable PE

11. Architectural model Characterization Switch Switch Switch Switch • The Systolic Ring Architectural model • Based on a coarse-grained configurable PE • Circular datapaths Dnode Dnode Dnode Dnode Dnode Dnode Dnode Dnode

12. Architectural model Characterization Switch Switch Switch Switch • The Systolic Ring Architectural model • Based on a coarse-grained configurable PE • Circular datapaths • 3 parameters • C: # of layers • N: # of Dnodes per layer layer 1 Dnode Dnode layer 4 Dnode Dnode Dnode Dnode layer 2 Dnode # of layers : 4 (C = 4) # of Dnode per layer : 2 (N = 2) Dnode layer 3

13. Architectural model Characterization • The Systolic Ring Architectural model • Based on a coarse-grained configurable PE • Circular datapaths • 3 parameters • C: # of layers • N: # of Dnodes per layer layer 1 layer 2 layer 8 layer 3 layer 7 layer 4 # of layers : 8 (C = 8) # of Dnode per layer : 2 (N = 2) layer 6 layer 5

14. Architectural model Characterization • The Systolic Ring Architectural model • Based on a coarse-grained configurable PE • Circular datapaths • 3 parameters • C: # of layers • N: # of Dnodes per layer • S: # of Rings layer 1 layer 2 layer 8 layer 3 layer 7 layer 4 # of layers : 8 (C = 8) # of Dnode per layer : 2 (N = 2) 1 Systolic Ring (S = 1) layer 6 layer 5

15. Architectural model Characterization • The Systolic Ring Architectural model • Based on a coarse-grained configurable PE • Circular datapaths • 3 parameters • C: # of layers • N: # of Dnodes per layer • S: # of Rings # of layers : 4 (C = 4) # of Dnode per layer : 2 (N = 2) 4 Systolic Ring (S = 4)

16. Architectural model Characterization • The Systolic Ring Architectural model • Based on a coarse-grained configurable PE • Circular datapaths • 3 parameters • C: # of layers • N: # of Dnodes per layer • S: # of Rings • Control Units • Local Dnodes units Dnode Sequencer

17. Architectural model Characterization • The Systolic Ring Architectural model • Based on a coarse-grained configurable PE • Circular datapaths • 3 parameters • C: # of layers • N: # of Dnodes per layer • S: # of Rings • Control Units • Local Dnode unit • Local Ring unit Local Ring Sequencer Local Ring Sequencer Local Ring Sequencer Local Ring Sequencer

18. Architectural model Characterization • The Systolic Ring Architectural model • Based on a coarse-grained configurable PE • Circular datapaths • 3 parameters • C: # of layers • N: # of Dnodes per layer • S: # of Rings • Control Units • Local Dnode unit • Local Ring unit • Global unit Global Sequencer Local Ring Sequencer Local Ring Sequencer Local Ring Sequencer Local Ring Sequencer

19. Architectural model Characterization • Remanence • Only one Systolic Ring S=1 • NPE = # of Dnodes = N*C*S = N*C • Remanence formalisation • k= C/N

20. Architectural model Characterization • A(NPE) formalisation for OD(NPE) • 0.18µ CMOS technology • C = 4, N = 2, S = 1 • A(8) = 3.3 mm ² • A(8) = 407M ² • Area formalisation: • A ( NPE ) = f ( N, C, S ) • depends on C / N ratio and S • NPE = N.C.S Systolic Ring layout (C=4, N=2, S=1) Area formalisation calibrated on these results

21. Architectural model Characterization • OD(NPE) for 1 Systolic Ring (S=1) • k = C/N = [ 0.25 ; 4 ] • decreasing OD(NPE) • OD(NPE) for several Systolic Ring • k = C/N = 4 • multi-ring instanciations increase scalability

22. Architectural model Characterization • Customisation and design technique • between 60 and 80 processing elements

23. Architectural model Characterization • Customisation and design technique • between 60 and 80 processing elements

24. Architectural model Characterization • Customisation and design technique Design Space

25. Architectural model Characterization Best OD and remanence Worst interconnect resources and processing power Design Space

26. Architectural model Characterization Worst OD and remanence Best interconnect resources and processing power Design Space

27. Architectural model Characterization R and OD can be integrated in CAD tools to observe architectural parameters effects and choose best trade-offs in the design space

28. Conclusion and perspectives IP 1 IP 2 IP 3 IP n R1 OD1 R2 OD2 R3 OD3 Rn ODn Specifications Processing power Area Power consumption etc.

29. Conclusion and perspectives IP 1 IP 2 IP 3 IP n R1 OD1 R2 OD2 R3 OD3 Rn ODn Architectural models Comparisons Specifications Processing power Area Power consumption etc.

30. Conclusion and perspectives IP 1 IP 2 IP 3 IP n R1 OD1 R2 OD2 R3 OD3 Rn ODn Architectural model Customisation Specifications Processing power Area Power consumption etc.

31. Thank You