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Reconfigurable computing

Reconfigurable computing. Papers: [Goldstein et al] PipeRench: A Coprocessor for Streaming Multimedia Acceleration [Razdan & Smith] PRISC: A High-Performance Microarchitecture with PFUs [Cardoso & Vestias] Architectures and Compilers to Support Reconfigurable Computing. Terminology.

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Reconfigurable computing

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  1. Reconfigurable computing Papers: [Goldstein et al] PipeRench: A Coprocessor for Streaming Multimedia Acceleration [Razdan & Smith] PRISC: A High-Performance Microarchitecture with PFUs [Cardoso & Vestias] Architectures and Compilers to Support Reconfigurable Computing

  2. Terminology FPGA Field Programmable Gate Array PFU Programmable Functional Unit ISA Instruction Set Architecture PE Processing Element PRISC PRogrammable Instruction Set Computer RPU Reconfigurable Processing Unit

  3. Challenge 1 Workloads submitted to processorsinclude more and more simple calculationson very large quantities of data. Multimedia applications, video streaming…

  4. Challenge 1 Assumptions of general purpose processing: The processor reads more instructions than data elements processors are optimized for high instructions bandwidth (pre-fetching, branch prediction) Data comes in fixed sized, wide words 32 or 64 bits are not uncommon

  5. Challenge 1 Characteristics of data stream processing : Data comes in large quantities of variable, small width elements 12 bits, 7 bits… A single transformation is to be applied to all the data elements That transformation is domain specific and is likely torequire several instructions on a general-purpose processor

  6. Challenge 2 Performance critical applicationsoften rely on a reduced number of functions being executed frequently Can we support those in hardware?

  7. Reconfigurable computing Papers: [Goldstein et al] PipeRench Challenge 1 [Razdan & Smith] PRISC Challenge 2 [Cardoso & Vestias] Challenge 2

  8. Idea Design hardware that can be configuredat run time to support: Complex transformations of datain a single clock cycle Variable data widths (challenge 1)

  9. Approaching the Solution Goldstein

  10. Approaching the Solution Cardoso

  11. Designing the Solution Goldsteinattached processor

  12. Designing the Solution Razdnfunctional unit

  13. Designing the Solution Razdnfunctional unit

  14. Designing the Solution Cardosofunctional unit

  15. Hardware Costs Cardoso

  16. Impact on Compiling Razdn

  17. So, why don’t I have one yet? Shortcomings of FPGAs [Goldstein et al]: Configuration time – 100s of microsecs to 100s of millisecs Forward compatibility – must be redesigned every generation Compilation time – synthesis, placement and routing Logic granularity – designed to replace random logic Hard constraints – the hardware image must fit

  18. Comparison in a typical application

  19. PRISC performance Applicability and application speedup

  20. PipeRench performance Performance on benchmark kernels:

  21. PipeRench performance Performance on applications:

  22. Conclusion PipeRench PRISC

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