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EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality?

EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality?. April 7, 2011. EDA360. Three Key Pillars of EDA360. System Realization. SoC Realization. Silicon Realization. EDA360. Three Key Pillars of EDA360. System Realization. SoC Realization. Silicon Realization. EDA360.

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EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality?

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  1. EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 7, 2011

  2. EDA360 Three Key Pillars of EDA360 System Realization SoC Realization Silicon Realization

  3. EDA360 Three Key Pillars of EDA360 System Realization SoC Realization Silicon Realization

  4. EDA360 Three Key Pillars of EDA360 System Realization SoC Realization Traditional EDA, including all the required technologies to design, verify, and implement silicon, packages, and boards Silicon Realization

  5. EDA360 Three Key Pillars of EDA360 System Realization Software content (IP), tools, and services that enable the delivery, integration, and support of high-quality IP required in complex SoCs SoC Realization Traditional EDA, including all the required technologies to design, verify, and implement silicon, packages, and boards Silicon Realization

  6. EDA360 Three Key Pillars of EDA360 Software content (IP), tools, and services that enable hardware-aware system development and verification System Realization Software content (IP), tools, and services that enable the delivery, integration, and support of high-quality IP required in complex SoCs SoC Realization Traditional EDA, including all the required technologies to design, verify, and implement silicon, packages, and boards Silicon Realization

  7. Silicon Realization – Customer Challenges • Time to market • Disaggregated, global design chainlimits visibility and predictability forcomplex designs – causingschedule delays and respins • Lack of true holistic and integratedsilicon-package-board flowscauses productivity gap • Reuse • Profitability • Design failure catastrophic • Functionality, performance, and power improvements contribute to higher margins • Manufacturability

  8. System Realization – Customer Challenges • Software development trails hardware development, impacting time-to-market • Hardware-software integration complexity impeding product shipments, quality • Effective and predictable system and sub-system verification

  9. System Realization – Market LandscapeDevelopment costs rising Software Millions HW Design andVerification HW Implementationand Manufacturing Source: IBS 2009

  10. System Realization – Market LandscapeMarket window shrinking; growing penalties for delay Source: IBS Percent Revenue Loss

  11. Sample Challenges at Each Realization Layer Application Application Application Application Application Framework / GUI Libraries O/S Runtimes System O/S Hardware System Architecture Drivers IP Configuration Test Programs SoC Scheduler … PowerManagement Mixed Signal Low Power Advanced Node Silicon DFM Giga-Gates/GHz Verification

  12. EDA360 – The Technical Version Common Design Database

  13. EDA360 – The Technical Version Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc.

  14. EDA360 – The Technical Version Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools)

  15. EDA360 – The Technical Version Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  16. EDA360 – The Technical Version Silicon Realization Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  17. EDA360 – The Technical Version Silicon Realization Chip (Spec to GDSII) Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  18. EDA360 – The Technical Version Silicon Realization Chip (Spec to GDSII) Digital Flow (GigaGates/GHz) Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  19. EDA360 – The Technical Version Silicon Realization Chip (Spec to GDSII) Digital Flow (GigaGates/GHz) Mixed-Signal Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  20. EDA360 – The Technical Version Silicon Realization Chip (Spec to GDSII) Digital Flow (GigaGates/GHz) Mixed-Signal Flow RF Sub Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  21. EDA360 – The Technical Version Silicon Realization Chip (Spec to GDSII) Digital Flow (GigaGates/GHz) Mixed-Signal Flow RF Sub Flow Custom/Analog Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  22. EDA360 – The Technical Version Silicon Realization Chip (Spec to GDSII) Digital Flow (GigaGates/GHz) Mixed-Signal Flow RF Sub Flow Custom/Analog Flow Low-Power Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  23. EDA360 – The Technical Version Silicon Realization Chip (Spec to GDSII) Package Digital Flow (GigaGates/GHz) Mixed-Signal Flow RF Sub Flow Custom/Analog Flow Low-Power Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  24. EDA360 – The Technical Version Silicon Realization Chip (Spec to GDSII) Package Digital Flow (GigaGates/GHz) Single Chip Mixed-Signal Flow RF Sub Flow Custom/Analog Flow Low-Power Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  25. EDA360 – The Technical Version Silicon Realization Chip (Spec to GDSII) Package Digital Flow (GigaGates/GHz) Single Chip Mixed-Signal Flow RF Sub Flow Multi Chip Custom/Analog Flow Low-Power Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  26. EDA360 – The Technical Version Silicon Realization Chip (Spec to GDSII) Package Digital Flow (GigaGates/GHz) Single Chip Mixed-Signal Flow RF Sub Flow Multi Chip Custom/Analog Flow 2.5D And 3D Low-Power Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  27. EDA360 – The Technical Version Silicon Realization Chip (Spec to GDSII) Package Board Digital Flow (GigaGates/GHz) Single Chip Mixed-Signal Flow RF Sub Flow Multi Chip Custom/Analog Flow 2.5D And 3D Low-Power Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  28. EDA360 – The Technical Version Silicon Realization Chip (Spec to GDSII) Package Board Digital Flow (GigaGates/GHz) Layout and Routing Single Chip Mixed-Signal Flow RF Sub Flow Multi Chip Custom/Analog Flow 2.5D And 3D Low-Power Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  29. EDA360 – The Technical Version Silicon Realization Chip (Spec to GDSII) Package Board Digital Flow (GigaGates/GHz) Layout and Routing Single Chip Mixed-Signal Flow AMS Simulation RF Sub Flow Multi Chip Custom/Analog Flow 2.5D And 3D Low-Power Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  30. EDA360 – The Technical Version Silicon Realization Chip (Spec to GDSII) Package Board Digital Flow (GigaGates/GHz) Layout and Routing Single Chip Mixed-Signal Flow AMS Simulation RF Sub Flow Multi Chip Signal and Power Integrity Custom/Analog Flow 2.5D And 3D Low-Power Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  31. EDA360 – The Technical Version Silicon Realization Chip (Spec to GDSII) Package Board Digital Flow (GigaGates/GHz) Layout and Routing Single Chip Mixed-Signal Flow AMS Simulation RF Sub Flow Multi Chip Signal and Power Integrity Custom/Analog Flow 2.5D And 3D FPGA and PCB Codesign Low-Power Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  32. EDA360 – The Technical Version SoC Realization Silicon Realization Chip (Spec to GDSII) Package Board High-Quality IP Digital Flow (GigaGates/GHz) Layout and Routing Single Chip Mixed-Signal Flow AMS Simulation RF Sub Flow Multi Chip Signal and Power Integrity Custom/Analog Flow 2.5D And 3D FPGA and PCB Codesign Low-Power Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  33. EDA360 – The Technical Version SoC Realization Silicon Realization Chip (Spec to GDSII) Package Board High-Quality IP Digital Flow (GigaGates/GHz) Design IP Layout and Routing Single Chip Synthesizable (Soft) Mixed-Signal Flow AMS Simulation Process-Specific (Hard) RF Sub Flow Multi Chip Signal and Power Integrity Custom/Analog Flow 2.5D And 3D FPGA and PCB Codesign Low-Power Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  34. EDA360 – The Technical Version SoC Realization Silicon Realization Chip (Spec to GDSII) Package Board High-Quality IP Digital Flow (GigaGates/GHz) Design IP Layout and Routing Single Chip Synthesizable (Soft) Mixed-Signal Flow AMS Simulation Process-Specific (Hard) RF Sub Flow Multi Chip Signal and Power Integrity Custom/Analog Flow Verification IP 2.5D And 3D FPGA and PCB Codesign Low-Power Flow Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  35. EDA360 – The Technical Version SoC Realization Silicon Realization Chip (Spec to GDSII) Package Board High-Quality IP Digital Flow (GigaGates/GHz) Design IP Layout and Routing Single Chip Synthesizable (Soft) Mixed-Signal Flow AMS Simulation Process-Specific (Hard) RF Sub Flow Multi Chip Signal and Power Integrity Custom/Analog Flow Verification IP 2.5D And 3D FPGA and PCB Codesign Low-Power Flow IP-Centric Design Environment Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  36. EDA360 – The Technical Version System Realization SoC Realization Silicon Realization Chip (Spec to GDSII) Package Board High-Quality IP Digital Flow (GigaGates/GHz) Design IP Layout and Routing Single Chip Synthesizable (Soft) Mixed-Signal Flow AMS Simulation Process-Specific (Hard) RF Sub Flow Multi Chip Signal and Power Integrity Custom/Analog Flow Verification IP 2.5D And 3D FPGA and PCB Codesign Low-Power Flow IP-Centric Design Environment Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  37. EDA360 – The Technical Version System Realization SoC Realization Silicon Realization Chip (Spec to GDSII) Package Board High-Quality IP Apps Middleware OS Drivers Digital Flow (GigaGates/GHz) Design IP Layout and Routing Single Chip Synthesizable (Soft) Mixed-Signal Flow AMS Simulation Process-Specific (Hard) RF Sub Flow Multi Chip Signal and Power Integrity Custom/Analog Flow Verification IP 2.5D And 3D FPGA and PCB Codesign Low-Power Flow IP-Centric Design Environment Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  38. EDA360 – The Technical Version System Realization SoC Realization Silicon Realization Chip (Spec to GDSII) Package Board High-Quality IP Apps Middleware OS Drivers Digital Flow (GigaGates/GHz) Design IP Layout and Routing Single Chip Hardware-Aware Software Development Environment Synthesizable (Soft) Mixed-Signal Flow AMS Simulation Process-Specific (Hard) RF Sub Flow Multi Chip Signal and Power Integrity Custom/Analog Flow Verification IP 2.5D And 3D FPGA and PCB Codesign Low-Power Flow IP-Centric Design Environment Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  39. EDA360 – The Technical Version System Realization SoC Realization Silicon Realization Chip (Spec to GDSII) Package Board High-Quality IP Apps Middleware OS Drivers Digital Flow (GigaGates/GHz) Design IP Layout and Routing Single Chip Hardware-Aware Software Development Environment Synthesizable (Soft) Mixed-Signal Flow System-Level Hardware Design Environment AMS Simulation Process-Specific (Hard) RF Sub Flow Multi Chip Signal and Power Integrity Custom/Analog Flow Verification IP 2.5D And 3D FPGA and PCB Codesign Low-Power Flow IP-Centric Design Environment Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  40. EDA360 – The Technical Version System Realization SoC Realization Silicon Realization Chip (Spec to GDSII) Package Board High-Quality IP Apps Middleware OS Drivers Digital Flow (GigaGates/GHz) Design IP Layout and Routing Single Chip Hardware-Aware Software Development Environment Synthesizable (Soft) Mixed-Signal Flow System-Level Hardware Design Environment AMS Simulation Process-Specific (Hard) RF Sub Flow Multi Chip Signal and Power Integrity Virtual Prototyping Environment System-Level Simulation System-Level Emulation Custom/Analog Flow Verification IP 2.5D And 3D FPGA and PCB Codesign Low-Power Flow IP-Centric Design Environment Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  41. EDA360 – The Technical Version System Realization SoC Realization Silicon Realization Chip (Spec to GDSII) Package Board High-Quality IP Apps Middleware OS Drivers Digital Flow (GigaGates/GHz) Design IP Layout and Routing Single Chip Hardware-Aware Software Development Environment Synthesizable (Soft) Mixed-Signal Flow System-Level Hardware Design Environment AMS Simulation Process-Specific (Hard) RF Sub Flow Multi Chip Signal and Power Integrity Virtual Prototyping Environment System-Level Simulation System-Level Emulation Custom/Analog Flow Verification IP 2.5D And 3D FPGA and PCB Codesign Low-Power Flow IP-Centric Design Environment System-Level Verification Common Design Database Design Intent (Power, Pinout, Signal Integrity, Jitter, Cost, Use Cases, Etc. Design Abstraction (models have multiple abstraction views for different tools) Design Convergence (Get to the final design in an iterative but deterministic way)

  42. EDA360 Case Study: Agilent InfiniiVision Digital/Mixed-Signal Sampling Oscilloscope Note: This case study is based on public, published data and nothing is implied about the EDA tools used to develop this product. Reproduced with Permission, Courtesy of Agilent Technologies, Inc.

  43. Agilent InfiniiVision 2000/3000 DSO/MSO System Block Diagram Measurement and Search Acceleration* Measurement Buffer (64K) User Interface Host Processor A/D Converter Acquisition Memory Manager Display Plotter LCD Panel Analog Signals Digital Signals DRAM ADC Data DRAM Hardware Serial Decoders (Simultaneous) GUI Controller Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Mask * 23 automated measurements such as voltage, time, and frequency as well as four waveform math functions including FFT Trigger Waveform Synthesis Diagram as published in EE Times

  44. Agilent InfiniiVision 2000/3000 DSO/MSO System Intent Measurement and Search Acceleration Measurement Buffer (64K) User Interface Host Processor 4 Gbytes/sec A/D Converter Acquisition Memory Manager Display Plotter LCD Panel Analog Signals Digital Signals DRAM ADC Data DRAM Hardware Serial Decoders (Simultaneous) GUI Controller Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) 2 Gbytes/sec Hardware Serial Decoders (Simultaneous) Mask Trigger Waveform Synthesis Diagram as published in EE Times

  45. Agilent InfiniiVision 2000/3000 DSO/MSO System Intent Measurement and Search Acceleration Measurement Buffer (64K) User Interface Host Processor 4 Gbytes/sec A/D Converter Acquisition Memory Manager Display Plotter LCD Panel Analog Signals Digital Signals DRAM ADC Data DRAM >4Gbytes/sec Hardware Serial Decoders (Simultaneous) GUI Controller Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) 2 Gbytes/sec Hardware Serial Decoders (Simultaneous) Mask Trigger Waveform Synthesis Diagram as published in EE Times

  46. Agilent InfiniiVision 2000/3000 DSO/MSO System Intent Measurement and Search Acceleration Measurement Buffer (64K) User Interface Host Processor 4 Gbytes/sec A/D Converter Acquisition Memory Manager Display Plotter LCD Panel Analog Signals Digital Signals DRAM ADC Data DRAM >>4Gbytes/sec >4Gbytes/sec Hardware Serial Decoders (Simultaneous) GUI Controller Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) 2 Gbytes/sec Hardware Serial Decoders (Simultaneous) Mask Trigger Waveform Synthesis Diagram as published in EE Times

  47. Agilent InfiniiVision 2000/3000 DSO/MSO System Partitioning Measurement and Search Acceleration Measurement Buffer (64K) MegaZoom IV SoC Processor running Win CE A/D Converter Acquisition Memory Manager Display Plotter LCD Panel Analog Signals Digital Signals DRAM ADC Data DRAM Hardware Serial Decoders (Simultaneous) GUI Controller Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Mask Trigger Waveform Synthesis Diagram as published in EE Times

  48. Agilent InfiniiVision 2000/3000 DSO/MSO System Partitioning Measurement and Search Acceleration Measurement Buffer (64K) MegaZoom IV SoC Processor running Win CE A/D Converter Acquisition Memory Manager Display Plotter LCD Panel Analog Signals Digital Signals DRAM ADC Data DRAM Hardware Serial Decoders (Simultaneous) GUI Controller Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) Hardware Serial Decoders (Simultaneous) On-chip DRAM allows wide, high-bandwidth connections On-Chip DRAM allows High-Bandwidth Connections Mask Trigger Waveform Synthesis Diagram as published in EE Times

  49. Agilent MegaZoom IV SoC Reproduced with Permission, Courtesy of Agilent Technologies, Inc.

  50. Agilent InfiniiVision 2000 X-Series DSO Circuit Board Image courtesy of David Jones, www.eevblog.com

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