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Meeting on Radiation Tolerant Electronics DAQ

Meeting on Radiation Tolerant Electronics DAQ. Csaba Soós 30 August, 200 4. DDL RadTol Project. The project has been started in 1998 The main goal of the project is to test COTS components that are going to be used for the DDL Collaboration between: CERN

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Meeting on Radiation Tolerant Electronics DAQ

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  1. Meeting on Radiation Tolerant ElectronicsDAQ Csaba Soós 30 August, 2004 Meeting on Radiation Tolerant Electronics - DAQ

  2. DDL RadTol Project • The project has been started in 1998 • The main goal of the project is to test COTS components that are going to be used for the DDL • Collaboration between: • CERN • KFKI – Research Institute for Particle and Nuclear Research, Budapest • Institute of Nuclear Research (ATOMKI), Debrecen • Technical University of Budapest • Royal Institute of Technology, Stockholm • Test facilities: • Debrecen, Hungary (gamma and neutron) • Uppsala, Sweden (proton) Meeting on Radiation Tolerant Electronics - DAQ

  3. RadTol Project Results (1/2) • Crystal oscillators (Pletronics, Saronix, CFP, Ecliptek) • TID 100 krad: negligible waveform change, no degradation • Voltage regulators • Micrel: increased noise (< 6 mV), noise peaks (20 mVpp), permanent damage (voltage shift) at 100 krad • Linear Technology: increased noise (< 6 mV), no damage • Electrical transceivers: • Vitesse (GaAs): no damage up to 140 krad, 0 error @ 1012 n/cm2 • Texas Instruments (CMOS): no damage up to 400 krad • Optical transceivers: • Agilent: no damage up to 22.8 krad, 13 error @ 1012 n/cm2 • Infineon: no damage up to 28.5 krad, 6 error @ 1012 n/cm2 Meeting on Radiation Tolerant Electronics - DAQ

  4. RadTol Project Results (2/2) • Altera APEX-E (0.18 m CMOS) SRAM-based • σconfiguration cell: 4.90 – 8.20 · 10-13 cm2/LC @ 180 MeV (p) 1.66 – 7.06 · 10-14 cm2/LC @ 5-14 MeV (n) • σmemory cell: 3.08 – 4.24 · 10-14 cm2/bit @ 180 MeV (p) 4.64 – 5.86 · 10-14 cm2/bit @ 100 MeV (p) 2.90 – 5.09 · 10-15 cm2/bit @ 5-14 MeV (n) • Xilinx Virtex II (0.15 m CMOS) SRAM-based • σ configuration cell: 4.5 – 9.0 · 10-13 cm2/LC @ 171 MeV (p) 5.5 – 10.2 · 10-13 cm2/LC @ 94 MeV (p) 5.5 – 10.7 · 10-13 cm2/LC @ 48 MeV (p) • Actel ProASIC+ (0.25 m CMOS) Flash-based • σ logic tile: < 2.03 · 10-13 cm2/LC @ 171 MeV (p) < 1.19 · 10-13 cm2/LC @ 94 MeV (p) < 0.71 · 10-13 cm2/LC @ 48 MeV (p) • TID: temporary damage at 12 krad; device has been recovered after one hour at room temperature. Meeting on Radiation Tolerant Electronics - DAQ

  5. Current DDL Design (ALTERA) Covered by CRC Type of error: BER + CL BER BER Data path(2x16 bits)+ control Data path(serial) Altera APEX 20K60E SERDES OpticalTransceiver Conf. EPROM BER bit error rate CL configuration loss Meeting on Radiation Tolerant Electronics - DAQ

  6. Problem • Present DDL implemented with ALTERA APEX-E(currently EP20K60E 160 kgates - 0.18 ) • Amongst all consequences of radiation, one is really problematic:the loss (or corruption) of the device configuration (= configuration cell changes its state due to high-energy particle interacting with the device) • Radiation tests have shown that we should expect 1 loss of configuration in 1 of the 400 DDL SIUs every hour • With the present design, some of these loss will not be detected Meeting on Radiation Tolerant Electronics - DAQ

  7. Solutions No simple solution.  To be worked out in details to understand all consequences. Two basic options: • Detect and fix the problem • Use a SRAM-based FPGA signaling loss of configuration (Altera) • Use a SRAM-based FPGA allowing to check the configuration (Xilinx) • Cure the problem in the implementation • Use a flash-based FPGA (e.g. ACTEL) • Use another rad-tol technology to implement the logic technology (ASIC) Meeting on Radiation Tolerant Electronics - DAQ

  8. SRAM-based FPGA – ALTERA ALTERA Cyclone • Easy porting from APEX to Cyclone (similar architecture) • Built-in error detection (CRC) • Error detection time can be as short as 1.8 ms • Reloading of the configuration takes 40-80 ms • Requires extra circuit (Flash-, or EEPROM-based CPLD) to monitor the configuration CRC and control the reconfiguration process • This extra circuit must be radiation tolerant (e.g. MAX 3000 family, 32 to 512 macrocells = logic array + register) Potential solution: EP1C6 (Cyclone) + MAX3000 TBD • Radiation test of Cyclone, MAX3000 and the new configuration memory devices • Design the logic in the MAX3000 • Define strategy for system recovery (impact on the software) Meeting on Radiation Tolerant Electronics - DAQ

  9. Possible Design with Cyclone Covered by CRC Type of error: BER +CL BER BER CRC_ERROR Altera CycloneEP1C6 MAXCPLD SERDES OpticalTransceiver Data path(2x16 bits)+ control Data path (Serial) Conf.EPROM configuration BER bit error rate CL configuration loss Meeting on Radiation Tolerant Electronics - DAQ

  10. SRAM-based FPGA – XILINX XILINX Virtex II • Easy porting from APEX • Configuration read back, and partial reconfiguration support • Reconfiguration can be done during operation • Internal open-drain drivers (majority voter for triple module redundancy) • Requires extra circuit (flash-, or eprom-based CPLD) to read and check the configuration (calculate CRC) + to control the SelectMAP interface • This extra circuit must be radiation tolerant • New design tools Potential solution: Virtex II + PLD TBD • Identify global solution, find the appropriate devices (size, complexity ?) • Check SelectMAP interface • Define strategy for system recovery (impact on DATE) Meeting on Radiation Tolerant Electronics - DAQ

  11. Possible Design with Virtex II Covered by CRC Type of error: BER +CL BER BER SelectMAP Xilinx Virtex II? PLD(+ μC) SERDES OpticalTransceiver Data path(2x16 bits)+ control Data path (Serial) Conf.EPROM BER bit error rate CL configuration loss Meeting on Radiation Tolerant Electronics - DAQ

  12. Flash-based FPGA (ACTEL) ACTEL ProASIC+ • Irradiation tests encouraging: see previous presentation • Capacity: no problem to fit the DDL SIU in. (PQFP 208 pins 75k to 1Mgates) • Different architecture, there is no “push-button” solution • Learn the peculiarities of the ACTEL software tools • Port of ALTERA-specific modules (LPM library: FIFO memories) • Timing-critical modules to be re-engineered (framing/de-framing @ 110 MHz) • Special voltage (+16 V and -13.8 V) required to reload configuration* • Additional hardware on the card for remote reconfiguration* (* in case remote configuration is needed) Potential solution: APA150 or APA300 TBD • Look in details to the port • Repeat TID test with lower dose rate Meeting on Radiation Tolerant Electronics - DAQ

  13. ProASIC+ Architecture • Smaller die size = less power consumption • Intrinsically hard switches (flash vs. SRAM) • Any 3-input, 1-output logic function(expect 3-input XOR) • Register/Latch with clear or set(enable requires additional cell) Meeting on Radiation Tolerant Electronics - DAQ

  14. Possible Design (ACTEL) Covered by CRC Type of error: BER Data path(2x16 bits)+ control BER BER Data path (Serial) Actel APA 150 or 300 SERDES OpticalTransceiver Power JTAG optional Note: device programming shouldn’t be performedduring beam activity (i.e. in radiation) to avoid SEL and SEGR BER bit error rate Meeting on Radiation Tolerant Electronics - DAQ

  15. Conclusion • Several COTS components have been tested over the last few years • SRAM-based FPGA is very sensitive to SEU • We have several potentially good solutions for the DDL SIU • To be worked out in details • None of them is simple • We continue the radiation tolerant tests, as well as the testing of new components and features Meeting on Radiation Tolerant Electronics - DAQ

  16. Meeting on Radiation Tolerant Electronics - DAQ

  17. Custom ASIC In-house developed ASIC • Intrinsically RadHard (no configuration, fixed routing) • Technically solid solution • Design has to be frozen • Porting is difficult and manpower intense • Different architecture and design method • Learn the peculiarities of ASIC design tools • Port the ALTERA-specific modules (multi-clocked FIFO) • Impact on the overall project schedule • Slightly more expensive Meeting on Radiation Tolerant Electronics - DAQ

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