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Overview on the development of front-end building blocks

Overview on the development of front-end building blocks. Eduard Atkin ( MEPhI ), Alexander Voronin (MSU). Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007. Outline. PART I – Design aspects Specifications Chip structure and building block list

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Overview on the development of front-end building blocks

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  1. Overview on the development of front-end building blocks Eduard Atkin (MEPhI), Alexander Voronin (MSU) Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  2. Outline PART I – Design aspects Specifications Chip structure and building block list Power consumption & ADC Derandomiser PART II – Test results CBM CSA prototype Derandomiser prototype UMC 0.18 rad tolerance Nucleon chip FSSR2 chip Outlooks Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  3. General specs for STS FEE • Accurate track reconstruction forces us to have: • Massive parallelism of read-out • High complexity (functionality) • Radiation hardness (tolerance) • Both amplitude and time processing • Mechanical (dimensional) fit (face-to-face) between strips and caseless ASICs • Low power (few (1-3!?) mW/channel) • Derandomisation (multiplexed readout) • Self-triggering (asynchronous scheme) CBM Collaboration Meeting, March 9-11, 2005 Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  4. STS readout technical requirements • Detector capacitance up to 70 pF (?) • Expected Detector pitch 50 µm  input chip pad pitch • Double sided detector  positive and negative polarities • AC coupled detector, DC coupling possibility • Minimal signal  1 MIP: 11000 e  150 µm detector thickness (?) 16500 e  200 µm realistic thickness with charge division (cluster) between neighbor strips 1 MIP can be 2-3 times less • Maximal signal  few MIPs (?)  3-6 bit ADC (8 bit?) • 1 MIP Signal/noise ratio  more than 12 (?) Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  5. STS readout technical requirements II • 100 ns double hit resolution • Time stamp resolution 2-4 ns (?) • Input current pulse duration 10 ns • Radiation hardness 1 Mrad (15?) • 2-4 mW/channel • Temperature 0…50oC (?) • Dead-time free • Self-triggered Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  6. Building blocks. Why we need them? Several groups use Cadence/Mentor Gr. software & UMC 0.18 µm Design Kits To safe man-power all we need a standard building block libraries “To make them is a lot of work. To test them even more”. (P.Fischer, Basic IPs in UMC018. 9th CBM Collaboration Meeting, GSI, 1.3.2007) Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  7. Simplified structure Analog part ADC Digital part Slow control Calibration (test) system Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  8. Building block list • Specs: • Power • Speed ADC Derandomizer Comparators How to build hierarchy? Slow Control • Different tasks: • Tracking • Calorimetry • Charge detection Driver CSA Opamp S/H Building Blocks Shaper PD T/H MUX Arbitration Logic HDR readout Control Logic Cross-point switch Data-driven readout Analog readout chain

  9. Low power pipeline ADC design*(toward ADC power reduction) done by A. Gumenjuk, V. Shunkov, Y. Bocharov, A. Simakov • 1st version: 7 bit&20 mW • 2nd version: 9 bit&8.5 mWprocess  UMC 0.18 µm Usually ADC is the most power-consuming part 2 ways to improve per channel power are:ￚto reduce power of ADC itself andￚ to provide analog multiplexing(derandomisation) and reduce the number of ADCs * Simulated, but not manufactured Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  10. 1020 um 420 um 7 bit 20 MSPS 20 mW ADC The 1st version of ADC consumed 20 mW and had 7 bits of resolution Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  11. Power efficient techniques • OpAmps and comparators beingshared between adjacent stages • Capacitors valuesscalingdownalong the pipeline • Using different OpAmps withsupply currents, scaled versus stage number • Redundant coding allows to usedynamic comparators withzerodc consumption Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  12. New OpAmp for back-end of pipeline The new class AB OpAmp consumesonly0.5 mA Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  13. Zero DC consumption comparator By using fully dynamic comparators the higher power efficiency was achieved Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  14. New 9 bit 20 MSPS 8.5 mW ADC • Lower power consumption, more then twice • Higher resolution • Lesser die area, more then twice • The first three stages are calibrated by OpAmps offset compensation • Shorter conversion latency – 6 cycles Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  15. New ADC features • Resolution 9 bits • Sampling Rate 20 MSPS • Power consumption 8.5 mW • Input capacitance 0.7 pF • Supply voltage 1.8 V • Process 0.18um MM/RF UMC CMOS Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  16. View on STS FEE Structure(toward reducing the number of ADCs) “Each FEE channel consists of three parts: analog front-end, digitization plus digital back-end” (from TSR, 2004). Any design, where each channel has its own ADC, is inefficient from the viewpoints of power consumptionandchip area (cost). That forces us to develop the data driven architecture based on the technique of derandomization. Example: FSSR2 chip Multichannel analog part ? Set of ADCs CBM Collaboration Meeting, March 9-11, 2005 Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  17. Derandomizer Analogderandomizeris a unit performing neuron-like processing, but in an analog field. It is a deadtime free analog unit withn-inputsandm-outputs,n>m. Thus it allows to reduce the number of following ADCs. The derandomization procedure implies the skipping of empty channels and thus is indivisibly bound with data sparcification. Efficient processing of the randomly appearing signals by blocks, having a dead time, needs the choice of a proper architecture. CBM Collaboration Meeting, March 9-11, 2005 Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  18. Derandomisation factor A necessary factor of derandomisation n/m may be estimated via ADC power consumption Example: If 1) power goal for ASIC is 2 mW/ch,2) one ADC power is 10 mW, 3) ADC consumes 50% of ASIC budget (1mW/ch), then the necessary derandomisation factor is 10. It means, that in average each ADC should process signals from 10 analog channels Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  19. Derandomiser structure Usually a derandomizer incorporates or is followed by such functional blocks as: • peak detectors (T&Hs) for amplitude measurement • time stamp • hit finder (fast low threshold LE discriminator) • arbitration logic • crosspoint switch • analog multiplexer CBM Collaboration Meeting, March 9-11, 2005 Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  20. Storage (T&H or PD) Preamps + Shapers IN1 MUX IN2 ADC ● ● ● ● ● ● INn CLK •bufferless  deadtime • long readout time Analog Storage + Analog Multiplex Example: Nucleon chip Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  21. Preamps +Shapers Multiple storage (interleavingT&H or PDs) Analogpipeline(SC memory) Preamps +Shapers Analog Memory + Analog Multiplex IN1 IN1 MUX MUX IN2 IN2 ADC ADC Multiple Storage Devices ● ● ● ● ● ● ● ● ● ● ● ● INn INn CLK CLK • buffered • long readout time • high power consumption •deadtimeless • complex control • long readout time Example: NXYTER chip Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  22. Analog storage devices (T&H or PD) Analog storage devices (T&H or PD) Crosspoint switch ADCs Crosspoint switch ADCs To DSP ● ● ● ● ● ● Address Address IN1 IN1 IN2 IN2 ● ● ● ● ● ● ● ● ● ● ● ● INn INn Arbitration Arbitration Preamps + Shapers Comparators Preamps + Shapers Comparators Crosspoint Switch One storage per channel Multiple storages shared by channels To DSP Example: Prototype 4-->2 Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  23. Building blocks • Charge Sensitive Amp • Amplitude (slow) shaper • Timing (fast) shaper • Low offset high-speed comparator both for hit finder and ADC: both clocked and non-clocked options • Threshold DAC (6-8 bit) • Fast low-bit (4…6 or 8 bit ?) ADC • Analog Derandomizer (deadtime free analog unit with n-inputs and m-outputs, n>m), 42 prototype: peak detector arbitration logic crosspoint switch • Cascode opampRail-to-rail op amp (high speed buffer) • Current and voltage references • Common issues are: UMC 0.18 um, low power consumption, reasonable speed & chip area Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  24. CSA, comparator, Rail-to-rail opamp CBM CSA prototype CBM run of April 2005, UMC 0.18um Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  25. CSA specifications • Detector coupling: a) AC – capacitor is on the detector or b) DC – CSA built-in leakage current compensationIt should be possible to read-out Si-strip signals in both AC- and DC- coupling modes without saturation. CSA should withstand a maximum sensor leakage (dark) current as high as 1 μA • Dynamic range of a few MIPs; • Random input signal rate of several 100 kHz per channel; • Small signal – 7000 electrons per MIP; • Detector capacitance 30-100 pF; • Power consumption 1 mW/channel; • Rise time (CSA output) – 10-200 ns; • Signal-to-noise ratio better than 10 for 1 MIP; Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  26. 8 channel CSA structure Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  27. CSA test results CSA response Leakage current compensation Output response versus input charge Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  28. Rail-to-rail OP, Clocked comparator Typical parameters of the op amp at capacitive load of 2.5 pF : Power consumption – 1 mW; Unity gain frequency – 57 МГц; Open loop gain – 52 дБ; Phase margin – 60°. Loaded to 15 pF Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  29. Fast Operational Amplifier Large signal Floating gate dynamic load for input stage Power consumption 1 mW Small signal Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  30. 42 Derandomizer, ADC S/H, Damp, HR transistors Analog storage Devices ( PD) Crosspoint switch ● ● ● Address IN1 IN2 ● ● ● ● ● ● IN4 Clock Arbitration Comparators CBM run of April 2006, UMC 0.18 um Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  31. ADC building blocks A. Simakov, Yu. Bocharov, A. Gumenjuk, A. Poliakov S/H schematics Differential amplifier S/H transfer function Sampling the sinus signal 118 kHz Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  32. First prototype 4  2 (simulations) 2 outputs 4 inputs X0, X1, X2, X3 – analog inputs, Y0, Y1 – cross-point switch outputs Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  33. Principal issues of the derandomizer prototype What were simplified on the prototype? • Functionality • Speed (ns signal range) • Low power consumption (2-3 mW/ch) • Digital part scalability • Not optimised on cross talk, linearity, noise • No drivers at the chip pads (ESD only) • Step pulse responses (overlapped) from different channels are not well arbitrated • Peak detector is not optimized for HOLD mode (cap discharge) Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  34. Derandomizer block typical responses Cross-point switch Comparator • 1 – input • 2 –output • 3 – threshold level 1 1 3 1 2 2 Peak detector • 1 - inputs • 2 – outputs 3 • 1 – input • 2 –output • 3 – reset 1 2 Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  35. Derandomizer response on 4 input signals 4 signals (comparator outputs) 2 cross-point switch outputs (after amplification) Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  36. Rad-tolerance tests(toward evaluation of UMC 0.18 µm) Two effects studied:1)Threshold voltage shift 100-200 mV 2) Leakage currents ----------standard nMOS; -------------ELT A. Simakov, CBM Collaboration Meeting, Feb 28 – Mar 2, 2007 Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  37. HDR Nucleon chip* • High dynamic range (100pC), power 2mW/ch, 32 chs • 2005-2007 • AMIS 0.35 um CMOS • 4 iterations: 1) Analog, 16 CSAs (included in Europractice annual 2005 report), Feb 2005 2) Mixed-signal, 4+2(test), CSA+SH+T&H+MUX+Driver, Sep. 2006 3) Mixed-signal, 4+2(test), CSA+SH+T&H+MUX+Driver, improved, Feb. 2007 4) Mixed-signal, 32+2 (test), CSA+SH+T&H+MUX+Driver, deadline Apr 23, 2007 * Developed for Roscosmos Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  38. NUCLEON architecture Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  39. References Digital part From 4 (+2) to 32 (+2) channels 34 chs 6 chs Differential Current drivers Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  40. Design features CSA structure CSA/shaper response CSA tail adjustment Typical waveforms Output current driver Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  41. FSSR2, FERMILAB Readout chip for Silicon Strip Detector • 128 channels • 4mW/chan. • Shaping time • 65-125 ns • Noise • 240+35e/pF… • 220+24e/pF • 3-bit ADC • 0.25um CMOS • tested for: • 5 Mrad protons • 19.4 Mrad γ-rays • No bias applied • Time stamp Valerio Re, et al., ADC in each channel Programmable gain Flash ADC One analog channel • FSSR2 can be used for hard radiation prototyping tests until the CBM-XYTER is developed Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

  42. Outlooks • Developed are different building blocks mostly in UMC 0.18 and partially in AMIS 0.35 • We are thinking about incorporating them into the CBM-XYTER • We are looking forward to request R&D money from RF Ministries Workshop on Silicon Detector Systems for the CBM experiment at FAIR, April 18-20, 2007

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