Jet algorithm/FPGA

1. Jet algorithm/FPGA by Attila Hidvégi

2. Content • Jet algorithm • Jet-FPGA • Changes • Results • Analysing the inputs • Tests at RAL • Summary and Outlook

3. Jet algorithm • Last time: • A threshold is passed when the cluster sum is greater than (>) the threshold. DONE • Saturation flag in an RoI vector is set when the arithmetical value of a selected cluster sum is greater then or equal (>=) to 1023. According to the specification it is set when the cluster sum contains a saturated element.????? • Implementation of a design according to the specifications was tested. It raises some new questions: • Should we look at each cluster sum type, or would it be enough to just look at the 4x4 cluster sum? • Should the local maximum finding take saturations into consideration? • The jet algorithm has still not been tested with high statistics in the XC2V2000. However, before we make such tests we need to decide how we want the algorithm to work.

4. Changes to jet-FPGA • Some rearrangement of features. Utilization decreased from 82% to 67% (69% with normal optimization). • Simple changes to the jet algorithm (>= to >) increased the utilization to 74%. It needs more investigation. • Introducing thresholds for input values (same threshold for all channels) increased the latency by one 40 MHz clock cycle. An incoming value must be greater than (>) the threshold. Utilization increased to 86%. • Changing the meaning of saturation flag in the ROI vectors decreased the utilization to 80%. The saturation flag in an ROI vector is set if any of the cluster sums that the ROI is using contains an input element that was saturated.

5. Changes to jet-FPGA • G-Link is now working with LVDCI_33 as well. The problem was caused by Xilinx ISE 6.1, the 6.3 and above works fine. • Five G-Link bits are used now, as shown below. • All data streams are active in all JEM configurations. (FCAL streams are sending out parity bit, even if the JEM is not handling any FCALs.)

6. Jet-FPGA results • Device utilization summary: • Number of External IOBs 481 out of 624 77% • Number of LOCed External IOBs 481 out of 481 100% • Number of RAMB16s 28 out of 56 50% • Number of SLICEs 8685 out of 10752 80% • Number of BUFGMUXs 5 out of 16 31% • Number of DCMs 2 out of 8 25% • Number of TBUFs 1102 out of 5376 20%

7. Jet-FPGA power consumption

8. Jet-FPGA capacitor data

9. Analysing the inputs • Clk_des2_80MHz synchronized to clk_des1_80MHz: • It takes 25 ns for a signal to propagate from FF_1 to FF_3. • The working window for clk_des2_80MHz is narrow. • Clk_des2_80MHz is 180o phase shifted relative to clk_des1_80MHz: • It takes 12.5 ns for a signal to propagate from FF_1 fo FF_3. • The working window for clk_des2_80MHz is wide. • Operation mode is chosen by phase shifting the jet design by 12.5 ns. • Right now we use a clk_des2_80MHz which is synchronized to clk_des1_80MHz. This should be changed.

10. Analysing the inputs

11. Analysing the inputs • Conclusions: • In theory the delay-scan of clk_des2 is unnecessary, unless a module is malfunctioning. • If the clk_des2_80MHz is 180o phase shifted relative to clk_des1_80MHz, then the clk_des2 is not needed at all since we could use the falling edge of clk_des1_80MHz instead.

12. How to reduce latency • Currently all the stages above have 25 ns of latency. • By changing the phase of clk_des2_80MHz, we can save 12.5 ns. • The input thresholds don’t need 25 ns of delay. It can easily be reduced to 12.5 ns. • By sending out the jetmultiplicities to the backplane on the falling edge of clk_des1_40MHz, the RTDP data will arrive at the CMM 25 ns earlier. • We can reduce the total latency by 50 ns quite easily.

13. Tests at RAL • FIO mapping has been sorted out. • FIOs on the backplane have been verified.

14. Summary and Outlook • The jet algorithm needs to be tested with high statistics in this FPGA, including FCAL. Some decisions need to be made first. • Reduce latency.