Course Introduction Kundanpassade kretsar Custom Designed Integrated Circuits

1. Course Introduction Kundanpassade kretsarCustom Designed Integrated Circuits Lecturer/Examinator:Alf Johansson Senior Lecturer, Embedded Systemsalf.johansso@ing.hj.se 0705-43 98 44 / 15 74 78 All documents are stored in the PingPong activity: Custom Designed Integrated Circuits 5p –HT05 Custom Designed Integrated Circuits

2. Course introduction Kurslitteratur på svenska:VHDL för konstruktion.Lennart Lindh, Stefan Sjöholm. Studentlitteratur (ISBN 9144024711) Litterature in English:VHDL for designers. Stefan Sjoholm/Lennart LindhPrentice Hall (ISBN 0134734149) Reference book:Designers Guide To VhdlAshenden, PeterElsevier, UK, 2000 (ISBN 1558606742). Custom Designed Integrated Circuits

3. Course Introduction ScheduleLectures/exercises(2p): Tuesdays 15– 17 Wednesdays 8 - 10 Labs/Projects(1+2p): Wednesdays 13 – 17 ExaminationWritten exam + labs + project. Custom Designed Integrated Circuits

4. 1. Course introduction. Custom Designed Integrated Circuits. Custom Designed Integrated Circuits

5. Customer Integrated Circuits Field programmable ASIC FPGA PLD Gate Array Std Cell Full Custom SOC SOC CPLD PLD ASIC= Application Specific Integrated Circuit Gate Array= Prefabricated wafer with logic+added interconnections (metal layers). Vol > 10k Standard Cell = Library with components (e.g. gates, multiplexors, flip-flops). Precompiled on transistor level. Vol >100k Full Custom = Transistor level design. Used for analogue circuits. SOC = System On Chip (processors, memories, logic) FPGA = Field Programmable Gate Array. >1 milj gates! PLD = Programmable Logic Device CPLD = Complex PLD. <10k gates Custom Designed Integrated Circuits

6. Motivation for HDL (Hardware Description Language) More and more complex circuits require efficient design and verification methods. Technology independent. We have a rapid change in technology. Design on a higher abstraction level and automatic ”codegeneration” (synthesis). Standardised HDL enables use of IPs, Intellectual Properties. Design and verification/test in one environment (language). Using a HDL for design is as natural as using C or ADA instead of assembler. Custom Designed Integrated Circuits

7. VHDL VHSIC Hardware Description Language (VHSIC=Very High Speed Integrated Circuit) Initiated by DoD (Department of Defense) early 1980s Specified by Intermetrics (they also specified ADA) Standard IEEE 1076-1987 (VHDL-87, VHDL-93, VHDL-2000, VHDL-2002) Standard language for specification and modelling Subset of language for synthesis Custom Designed Integrated Circuits

8. Why use VHDL ? Technology independent => Technologies change during the life time of electronic products. Use automatic tools to implement new technologies. Modifiability => Easy to read, hierarchical and structured. Hierarchical => Structural VHDL (block diagrams). Abstraction levels => Behaviour, RTL and gate level. Supports concurrent and sequential language constructions (C only sequential). Reuse of designs and part of designs => components. Can be verified in a (technology independent) simulator. De facto standard for design (synthesis) => Synopsys. Custom Designed Integrated Circuits

9. Development flow Custom Designed Integrated Circuits

10. History 1 Signal generator Prototype Oscilloscope Verification with ”black box” prototype Custom Designed Integrated Circuits

11. History 2 Input signal file ”signal gener.” Computer model. Netlist prototype. Output signal file ”logic analyser” Verification with a schematics in the computer Custom Designed Integrated Circuits

12. History 3 VHDL Synthesis Netlist Prototype model Input signal file ”signal gener.” Output signal file ”logic analyser” Synthesis to gates and flip-flops Custom Designed Integrated Circuits

13. A B History 4 Computer VHDL ”prototype” VHDL component ”signal gener.” VHDL component ”logic analyser” Verification with a testbench (A and B) in the computer Custom Designed Integrated Circuits

14. a & sel sel 1 c a 1 0 c & b b 1 Synthesis Synthesis = Translate VHDL to logic Logic synthesis = Translate Boolean functions to gates RTL synthesis (Register Transfer Level) = Logic synthesis + sequential constructs to gates and flip flops. All clocking defined by designer. Behavioral synthesis = reuse of components (e.g. a common multiplier). Clocking defined by synthesis tools. Technology mapping Synthesis process(sel,a,b)beginif sel=’1’ then c<=b;else c<=a;end if;end process; Custom Designed Integrated Circuits

15. System Functional level Behavioural level RTL level clk res Logic level & & & VHDL abstraction levels Computer model information Higher abstraction levels conceal details. Custom Designed Integrated Circuits

16. Design domains and abstraction levels in Y Charts Behavioral domain Structural domain Algorithms Processors, mem Functional design Behavioral Registers, ALUs RTL Gates, Flip-Flops Boolean Transistors Transistor functions Transistor layout Cells, modules Chips, ASICs Physical design of chips Boards, MCM More details when we move towards center Physical domain Custom Designed Integrated Circuits

17. Design Process Representation in Y- Chart Structural domain Behavioral domain netlist Algorithms Processors, mem Synthesis Behavioral (VHDL) Registers, ALUs RTL (VHDL) Gates, Flip-Flops, muxes, adders Gates, FF Boolean Transistor functions Transistors Implementation(technology mapping) Transistor layout Cells, modules Chips, ASICs e.g. bit file Boards, MCM Physical domain Custom Designed Integrated Circuits

18. VHDL abstraction levels and hierarchies Behavioural level: Reuse of instantiated components. No architecture is required. Research area. Few tools on market. RTL (Register Transfer Level): Logic + sequential circuits like registers andstate machines. At RTL all registers are defined in VHDL code. Logic level: Boolean algebra or gate network. Compare abstraction levels with programming languages: UML – C – assembler –machine code Abstraction levels: Complexity not reduced but easier to understand. Design hierarchies: Comp1 Comp21 Comp22 Custom Designed Integrated Circuits

19. VHDL VHDL components: Central concept in VHDL. The components can be stored in libraries. A component can be a simple gate or a complex system like a microprocessor. The internal behavior can be concealed from the designer (black box) and only the component interface is shown. Entity: The entity declaration defines the interface between an entity and the environment. The entity name is the same as the component name. Architecture: An architecture defines the body of a component entity and specifies the behavior between inputs and outputs. An architecture is tied to one entity and one entity can have several architectures. Custom Designed Integrated Circuits

20. -- ****************************************-- My first VHDL program-- Kundanpassade kretsar HT 2001-- **************************************** Two hyphens -- indicate start of a comment for the rest of a line library ieee;use std_logic_1164.all;use std_logic_unsigned.all; library for signal types The entitydescribes the boarder of a component Let’s make a very simple VHDL program entity and_gate isend; port describes the input and output signals of a component.a and b are input signalsc is an output signalstd_logic describes signal type port (a,b: in std_logic,c: out std_logic); Component name: and_gate architecturertl of and_gate isbeginendrtl; c <= a and b; rtl is an arbitrary name of an architecture architecture describes what shall be done Signal c is assigned the boolean and of a and b Custom Designed Integrated Circuits

21. VHDL Syntax Exampleentity ex isport(a,b: in std_logic; c: out std_logic);end ex; Syntax (VHDL-93) entity <identifier_name> isport([signal]<identifier>:[mode]<type_indicator>; [signal]<identifier>:[mode]<type_indicator>; …… [signal]<identifier>:[mode]<type_indicator>);end[entity] <identifier_name>; <mode> = in, out, inout, bufferin: input signal to componentout: output signal from componentinout: bidirectional signalbuffer: output signal that can be read (out signal can’t be read!!!) Custom Designed Integrated Circuits

22. VHDL Syntax -- Exampleentity ex isport(a,b: in std_logic; c: out std_logic);end ex; architecture rtl ofex isbeginc <= not (a and b);end rtl; Syntax (VHDL-93) architecture <architecture_name> of<entity_identifier> is[<architecture_declarative_part>]begin<architecture_statement_part>end [architecture] <architecture_name>; Custom Designed Integrated Circuits

23. Logical operators not inverteda<=not b; and a<=b and c; nand a<=b nand ca<=not(b and c); or a<=b or c; nor a<=not(b or c); xor a<=not((b and c) or (not b and not c)); xnor a<=(b and c) or (not b and not c); (VHDL –93) Custom Designed Integrated Circuits

24. The three faces of VHDL VHDL has three different parts: • Concurrent VHDL (Parallell VHDL) • Sequential VHDL (Sekventiell VHDL) • Structural VHDL (Strukturell VHDL) Some constructs are only allowed in the concurrent part other constructs only in the sequential part. The syntax may differ in the different parts ( in order to show the differences). The timing is different in concurrent and sequential VHDL Concurrent withxxselect q<=awhen ”00”, bwhen”11, ’0’ when others; Sequential case xx is when ”00” => q<=a; when ”11” => q<=b; when others => q<=’0’; end case; Custom Designed Integrated Circuits

25. Concurrent VHDL The nature of hardware is parallel. A HDL must have features to describe the parallel behavior of hardware. In VHDL this is called ”concurrent VHDL”. Signal assignment Think of signals as physical connections Examples: a<=’0’; a<=bafter 10 ns; a<=b and c; a<=’0’, ’1’ after 20 ns, b after 30 ns; Syntax (VHDL –93) Signal assignment:<target_identifier>’<=’ <selected_expression>’;’ Syntax (VHDL –93) Signal assignment with delay:<target_identifier>’<=’ <selected_expression> ’after’ 10 ’ns’ ’;’ NB ”after” can’t be synthesised and is dismissed by synthesiser. Custom Designed Integrated Circuits

26. a b b1 a b2 10 20 30 40 50 60 70 [ns] b3 a 10 20 30 40 50 60 70 80 [ns] Concurrent VHDL. Delays Inertial delay (tröghets): Default in VHDL. Spikes are not propagated (if ’after’ is used).Often used in electronic component delays. Transport delay: Pulses are always propagated. Used for delay lines. Reject delay: Is used when spike filtering is not the same as the circuit delay (VHDL-93). Inertial delay is ignorded by synthesis tools. Transport delay will give errors (often). b1 <= a inertialafter 10 ns;b2 <= a transport after 10 ns;b3 <= a reject 4 ns inertial after 10 ns; Custom Designed Integrated Circuits

27. a b c a b c Concurrent VHDL. Assignment order Concurrency: Hardware is parallel in nature. VHDL has constructions for concurrency (e.g C has not but SystemC has). Concurrent constructions in VHDL are executed concurrently and the order in which the code is written is irrelevant. Concurrent commands in VHDL are event-controlled. architecture rtl ofex1 isbeginc <= b; b <= a;end rtl; architecture rtl ofex2 isbeginb <= a; c <= b;end rtl; Custom Designed Integrated Circuits

28. 30 ns+2 delta 57 ns+2 delta A & C D B D 30 ns+1 delta 57 ns+1 delta A C B 10 20 30 40 50 60 70 [ns] 10 20 30 40 50 60 70 [ns] Concurrent VHDL. Delta time Delta time is used for queuing up sequential events. Delta times are executed while the simulation clock is stopped. When combinational logic has 0 ns delay the simulator counts up one delta time for each assignment. The delta time will count up until all signals are stable. What happens with the assignment: q <= not q; ?? D<= not C;C<=A and B; Custom Designed Integrated Circuits

29. Concurrent VHDL. When statement -- Examplearchitecture rtl ofex isbeginq<= a when data=”00” elseb when data=”11” elsec;end rtl; Syntax When statement:<target>’<=’ <expression> [after<expression>] when <condition> else <expression> [after <expression>]; Several when else lines can be used! Custom Designed Integrated Circuits

30. -- Example-- Useful when statementarchitecture rtl ofthree_state isbegindbus0<= data0 when enable=’1’ else’Z’;end rtl; enable data dbus Concurrent VHDL. When statement Custom Designed Integrated Circuits

31. Concurrent VHDL. With statement -- Examplearchitecture rtl ofex isbegin with data select q<=a when ”00”, b when ”11”, c when others;end rtl; Syntax With statement:with <expression> select <target>’<=’ <expression> when <choose>; <expression> when <choose>; All possible <choices> must be enumerated! Remaining choices can be collected in when others! Custom Designed Integrated Circuits

32. Concurrent VHDL. Object, class and type ClassObjectType signal a: std_logic; Std_ulogic/std_logic: ’U’ – uninitialized (start value=left) ’X’ – forcing unknown ’0’ – forcing 0 ’1’ – forcing 1 ’Z’ – high impedence ’W’ – weak unknown ’L’ – weak 0 ’H’ – weak 1 ’-’ – don’t care Class • constant • variable • signal ”a wire”, time dependent constant a: std_logic_vector(3 downto 0):= ”1111”;signal b: std_logic_vector(7 downto 0);variable c: std_logic; TypeDatatypes to be used in this course: • integer NB: Length is implementation dependent!Use range! signal my_int: integer range 0 to 255; • std_ulogic • std_logic (resolved type of std_ulogic). Signal driver and resolve function (read the book!!). Every signal assignment in concurrent VHDL will create a driver. Two or more assignments of the same signal require resolved types. Custom Designed Integrated Circuits

33. Concurrent VHDL Type declarations of std_logic_vector:type std_logic_vector is array (natural range<>) of std_logic; Declaration.signal a_vect: std_logic_vector(7 downto 0); -- normal way to write with MSB to the leftsignal a_vect: std_logic_vector(0 to 7); -- LSB to the left signal a_vect: std_logic_vector(7 downto 0); a_vect<= ”10101010”; -- Note double quotation marks! a_vect<= b_vect; Slice of arraysignal a_vect: std_logic_vector(7 downto 0);signal b_vect: std_logic_vector(5 downto 0); -- length differs a_vect(0)<= ’1’; a_vect(0)<= b_vect(1); a_vect(7 downto 1)<=a_vect(6 downto 0); --Left shift one step! a_vect<=(1=>’0’, 4=>’0’, others =>’1’); Custom Designed Integrated Circuits

34. Concurrent VHDL. Vector assignment Concatinationsignal a_vect: std_logic_vector(7 downto 0);signal b_vect: std_logic_vector(5 downto 0); -- length differs a_vect<=”00” & b_vect; -- add two msb Aggregatesignal a_vect: std_logic_vector(7 downto 0);a_vect<=(others=>’0’); -- a_vect>=”00000000”a_vect<=(1=>’0’, 4=>’0’, others =>’1’); Bit string literalsa_vect<=B”11110000”; -- B”1111_0000” more readablea_vect<=X”FFA0”; Custom Designed Integrated Circuits

35. Concurrent VHDL. Operators Relational operators = equal /= not equal < less than > greater than <= less than or equal >= greater than or equal Can be used on integers and std_logic_vectors = and /= can be used on all defined data types Arithmetic operators + addition - subtraction * multiplication / division abs absolute value rem remainder mod modulus ** exponantiation These operators are predefined for integer and time.If std_logic_vector shall be used the operators must be defined in a package e.g. std_logic_unsigned. library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all Custom Designed Integrated Circuits

36. Internal signals No in, out etc! Concurrent VHDL. Internal signal. Init values Left-hand values The default init value is the left-hand value in the value list. e.g. for std_logic the init value is ’U’. Init in entity or architecture (Not for synthesis) entity ex isport(a: in std_logic:=’0’; b: out std_logic);end; architecture behv of ex issignal i1: std_logic:=’1’; signal i2,i3: std_logic:=’H’; signal i4: std_logic_vector(3 downto 0):=”0000”;begin ……..end; Custom Designed Integrated Circuits

37. Concurrent VHDL. Block statement The block statement can be used to make the text more readable. The scope of signals that are declared in a block is the block. Signals from a block can be loaded into the simulator as one unit. The block statement is a concurrent statement. architecture behav of ex is signal abegin addr_decode: blocksignal cs_b: std_logic; signal addr: std_logic_vector(3 downto 0);begin……..end block;end behav; Block declarations scope Custom Designed Integrated Circuits

38. Xilinx CPLD/FPGA Introduction to labexercises Mentor HDesigner VHDL source Compiler/Simulator Synthesis Mentor Leonardo Mentor Modelsim Netlist (.edif) Place & RouteLoad circuit Xilinx Foundation Custom Designed Integrated Circuits

39. FPGAs in the future? Miljons of gates. 10 miljon gates circuits soon available. Lower cost. Now 0,1 öre/gate. Soft IP (microcontrollers, DSPs, etc ) IP=Intellectual Properties. FPGAs with hard IP cores. E.g. microcontrollers and FPGA in one circuit (SOPC) . SOPC, System On Programmable Chip. Custom Designed Integrated Circuits

40. Moore’s law Moore’s law: The capacity ( e.g. # of gates) of integrated chips doubles every 18-20 months. circuits tools 108106 gap Custom Designed Integrated Circuits

41. a Q b VHDL Examples Ex 1. Design a XOR-gate with AND and OR functions (entity xorgate) that has 2 inputs and one output. Use std_logic as signal type. Custom Designed Integrated Circuits

42. VHDL Examples Ex 2. Design a multiplexor (entity MUX8) that has 8 inputs, 3 selection lines and 1 output. The output is three_state type. Use std_logic as signal type. a0-a7 8 Q s0-s2 3 E Custom Designed Integrated Circuits

43. VHDL Examples Ex 3. Design an inverter (entity openc) that has an output as in the figure below. Use std_logic as signal type. Vdd Q a Vss Custom Designed Integrated Circuits