NetFPGA Hands-on Training Day 1

1. Presented by: Adam Covington (Stanford University) Indiana University, Bloomington June 18 - 19, 2012 http://NetFPGA.org NetFPGA Hands-on TrainingDay 1

2. Tutorial Outline Background Introduction The NetFPGA Platform The Stanford Base Reference Router Motivation: Basic IP review Example: Reference Router running on the NetFPGA Infrastructure Tree Build System Scripts The Life of a Packet Through the NetFPGA Hardware Datapath Interface to software: Exceptions and Host I/O Implementation Module Template User Data Path Write Crypto NIC using a static key Simulation and Debug Write and Run Simulations for Crypto NIC Concluding Remarks

3. Section I: Motivation

4. NetFPGA = Networked FPGA A line-rate, flexible, open networking platform for teaching and research

5. NetFPGA consists of… NetFPGA 1G Board Four elements: • NetFPGA board • Tools + reference designs • Contributed projects • Community NetFPGA 10G Board

6. NetFPGA Board Comparison

7. NetFPGA board PC with NetFPGA 1GE FPGA 1GE 1GE Memory 1GE NetFPGA Board NetworkingSoftware running on a standard PC CPU Memory PCI A hardware accelerator built with a Field Programmable Gate Arraydriving Gigabit network links

8. Tools + Reference Designs Tools: • Compile designs • Verify designs • Interact with hardware Reference designs: • Router (HW) • Switch (HW) • Network Interface Card (HW) • Router Kit (SW) • SCONE (SW)

9. Contributed Projects More projects: http://netfpga.org/foswiki/NetFPGA/OneGig/ProjectTable

10. Community Wiki • Documentation • User’s Guide • Developer’s Guide • Encourage users to contribute Forums • Support by users for users • Active community - 10s-100s of posts/week

11. International Community Over 1,000 users, using 2,000 cards at 150 universities in 40 countries

12. NetFPGA’s Defining Characteristics • Line-Rate • Processes back-to-back packets • Without dropping packets • At full rate of Gigabit Ethernet Links • Operating on packet headers • For switching, routing, and firewall rules • And packet payloads • For content processing and intrusion prevention • Open-source Hardware • Similar to open-source software • Full source code available • BSD-Style License • But harder, because • Hardware modules must meeting timing • Verilog & VHDL Components have more complex interfaces • Hardware designers need high confidence in specification of modules

13. Test-Driven Design • Regression tests • Have repeatable results • Define the supported features • Provide clear expectation on functionality • Example: Internet Router • Drops packets with bad IP checksum • Performs Longest Prefix Matching on destination address • Forwards IPv4 packets of length 64-1500 bytes • Generates ICMP message for packets with TTL <= 1 • Defines how packets with IP options or non IPv4 … and dozens more … Every feature is defined by a regression test

14. Who, How, Why Who uses the NetFPGA? • Teachers • Students • Researchers How do they use the NetFPGA? • To run the Router Kit • To build modular reference designs • IPv4 router • 4-port NIC • Ethernet switch, … Why do they use the NetFPGA? • To measure performance of Internet systems • To prototype new networking systems

15. Summer Camp Objectives • Overall picture of NetFPGA • How reference designs work • How you can work on a project • NetFPGA Design Flow • Directory Structure, library modules and projects • How to utilize contributed projects • Interface/Registers • How to verify a design (Simulation and Regression Tests) • Things to do when you get stuck AND… You can build your own projects!

16. Section II: Network review

17. Internet Protocol (IP) Data to be transmitted: Data … IP packets: IP Hdr IP Hdr IP Hdr Data Data Data … Ethernet Frames: Eth Hdr Eth Hdr Eth Hdr IP Hdr IP Hdr IP Hdr Data Data Data

18. Internet Protocol (IP) Data … 1 4 16 32 Ver HLen T.Service Total Packet Length Fragment ID Flags Fragment Offset IP Hdr Data 20 bytes TTL Protocol Header Checksum Source Address Destination Address Options (if any)

19. Basic operation of an IP router D R3 R1 R4 D A B E R2 C R5 Destination Next Hop F D R3 E R3 F R5

20. Basic operation of an IP router R3 R1 R4 D A B E R2 C R5 F

21. Forwarding tables 32 bits wide → ~ 4 billion unique address IP address Naïve approach: One entry per address ~ 4 billion entries Improved approach: Group entries to reduce table size

22. IP addresses as a line Your computer My computer Stanford Berkeley Asia North America 0 232-1 All IP addresses

23. Longest Prefix Match (LPM) Universities Continents Planet To: Stanford Data • Matching entries: • Stanford • North America • Everywhere Most specific

24. Longest Prefix Match (LPM) Universities Continents Planet To: Canada Data • Matching entries: • North America • Everywhere Most specific

25. Implementing Longest Prefix Match Searching Most specific FOUND Least specific

26. Basic components of an IP router Management & CLI Routing Protocols Software Control Plane Routing Table Data Plane per-packet processing Forwarding Table Switching Queuing Hardware

27. IP router components in NetFPGA Linux SCONE Management & CLI Management & CLI Routing Protocols OR Software Routing Protocols Routing Table Routing Table Router Kit Output Port Lookup Input Arbiter Output Queues Hardware Forwarding Table Switching Queuing

28. Section III: Example

29. Operational IPv4 router Java GUI SCONE Management & CLI Control Plane Software Routing Protocols Routing Table Reference router Forwarding Table Switching Queuing Data Plane per-packet processing Hardware

30. Streaming video

31. Streaming video NetFPGA running reference router PC & NetFPGA (NetFPGA in PC)

32. Streaming video Video streaming over shortest path Video client Video server

33. Streaming video Link breaks Video client Video server

34. Streaming video .1.1 .4.1 .7.1 .10.1 .13.1 .16.1 .1.2 .4.2 .7.2 .10.2 .13.2 .16.2 .3.1 .6.2 .9.2 .12.2 .15.2 .3.2 .6.1 .9.1 .12.1 .15.1 .30.2 .18.1 .30.1 .23.1 .18.2 .27.2 .24.2 .21.2 .24.1 .21.1 .27.1 .28.2 .25.2 .22.2 .19.2 .28.1 .25.1 .22.1 .19.1

35. Observing the routing tables • Columns: • Subnet address • Subnet mask • Next hop IP • Output ports

36. Demo

37. Review NetFPGA as IPv4 router: • Reference hardware + SCONE software • Routing protocol discovers topology Demo: • Ring topology • Traffic flows over shortest path • Broken link: automatically route around failure

38. Section IV: Infrastructure

39. Infrastructure • Tree structure • NetFPGA package contents • Reusable Verilog modules • Verification infrastructure • Build infrastructure • Utilities • Software libraries

40. Tree Structure (1) netfpga bin (scripts for running simulations and setting up the environment) bitfiles (contains the bitfiles for all projects that have been synthesized) lib (shared Verilog modules, libraries needed for simulation/synthesis/design) projects (user projects, including reference designs)

41. Tree Structure (2) lib C (common software and code for reference designs) java (contains software for the graphical user interface) Makefiles (makefiles for simulation and synthesis) (libraries to interact with reference designs, create test data, and manage simulations/regression tests) Perl5 python (common libraries to aid in regression tests) (utility scripts – less commonly used than those in the bin directory) scripts verilog (modules that can be reused in designs)

42. Tree Structure (3) projects/crypto_nic doc (project specific documentation) (XML files defining project and any local modules, auto-generated Verilog register defines) include lib (C/Perl defines for registers) (non-library Verilog code used for synthesis and simulation) src sw (software elements of the project) (project-specific .xco files to generate cores, Makefile to implement the design) synth test (simulation and hardware tests)

43. NetFPGA package contents • Projects: • HW: router, switch, NIC, buffer sizing router • SW: router kit, SCONE • Reusable Verilog modules • Verification infrastructure: • simulate full board with PCI + physical interfaces • run tests against hardware • test data generation libraries (eg. packets) • Build infrastructure • Utilities: • register I/O, packaging, … • Software libraries

44. Reusable Verilog modules

45. Verification Infrastructure • Simulation: nf_test.py sim • allows testing before synthesis • catches many bugs • Hardware tests: nf_test.py hw • test synthesized hardware • Test data generation libraries: • easily create test data: • many standard packet formats supported out of the box • easily add support for custom formats

46. Build infrastructure • Register system: • allocates memory to modules • generates “include” files for various languages • Build/synthesis: • required shared modules documented XML (shared with register system) • shared modules pulled in during synthesis • resultant bitfile checked for timing errors

47. Utilities • Bitfile download: nf_download • Register I/O: regread, regwrite • Device querying: nf_info • SRAM dumping: lib/scripts/sram_dump

48. Software libraries • Libraries for interfacing with NetFPGA: • C, Perl, Java, Python support

49. Section V: Life of a Packet

50. Reference Router Pipeline Five stages Input Input arbitration Routing decision and packet modification Output queuing Output Packet-based module interface Pluggable design MAC RxQ CPU RxQ MAC RxQ CPU RxQ MAC RxQ CPU RxQ MAC RxQ CPU RxQ Input Arbiter Output Port Lookup Output Queues MAC TxQ CPU TxQ MAC TxQ CPU TxQ MAC TxQ CPU TxQ MAC TxQ CPU TxQ