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NetFPGA Spring Camp Day 1

Presented by: Andrew W. Moore with Marek Michalski, Neelakandan Manihatty-Bojan, Gianni Antichi Georgina Kalogeridou, Jong Hun Han, Noa Zilberman aided by Yury Audzevich, Dimosthenis Pediaditakis Poznan University of Technology May 20 – 24, 2013 http://NetFPGA.org.

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NetFPGA Spring Camp Day 1

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  1. Presented by: Andrew W. Moore with Marek Michalski, Neelakandan Manihatty-Bojan, Gianni Antichi Georgina Kalogeridou, Jong Hun Han, Noa Zilberman aided by Yury Audzevich, Dimosthenis Pediaditakis Poznan University of Technology May 20 – 24, 2013 http://NetFPGA.org NetFPGA Spring CampDay 1

  2. Tutorial Outline Background Introduction The NetFPGA Platform The Base Reference Router Motivation: Basic IP review Example: Reference Router running on the NetFPGA Infrastructure Tree Build System Scripts The Life of a Packet Through the NetFPGA Hardware Datapath Interface to software: Exceptions and Host I/O Implementation Module Template Write Crypto NIC using a static key Simulation and Debug Write and Run Simulations for Crypto NIC Concluding Remarks

  3. Section I: Motivation

  4. NetFPGA = Networked FPGA A line-rate, flexible, open networking platform for teaching and research

  5. NetFPGA consists of… NetFPGA 1G Board Four elements: • NetFPGA board • Tools + reference designs • Contributed projects • Community NetFPGA 10G Board

  6. NetFPGA-10G • A major upgrade over the 1Gb/s predecessor • State-of-the-art technology

  7. 10 Gigabit Ethernet • 4 SFP+ Cages • AEL2005 PHY • 10G Support • Direct Attach Copper • 10GBASE-R Optical Fiber • 1G Support • 1000BASE-T Copper • 1000BASE-X Optical Fiber

  8. Others • QDRII-SRAM • 27MB • Storing routing tables, counters and statistics • RLDRAM-II • 288MB • Packet Buffering • PCI Express x8 • PC Interface • Expansion Slot

  9. Xilinx Virtex 5 TX240T • Optimized for ultra high-bandwidth applications • 48 GTX Transceivers • 4 hard Tri-mode Ethernet MACs • 1 hard PCI Express Endpoint

  10. NetFPGA Board Comparison

  11. Beyond Hardware • NetFPGA-10G Board • Xilinx EDK based IDE • Reference designs with ARM AXI4 • Software (embedded and PC) • Public Repository • Public Wiki GitHub, User Community MicroBlaze SW PC SW Xilinx EDK Reference Designs AXI4 IPs

  12. NetFPGA board PC with NetFPGA 10GE FPGA 10GE 10GE Memory 10GE NetworkingSoftware running on a standard PC CPU Memory PCIe A hardware accelerator built with a Field Programmable Gate Arraydriving 10 Gigabit network links

  13. Tools + Reference Designs Tools: • Compile designs • Verify designs • Interact with hardware Reference designs: • Router (HW) • Switch (HW) • Network Interface Card (HW) • Router Kit (SW) • SCONE (SW)

  14. Contributed Projects More projects: • https://github.com/NetFPGA/NetFPGA-public/wiki/Projects

  15. Community Wiki • Documentation • User’s Guide “so you just got your first NetFPGA” • Developer’s Guide “so you want to build a …” • Encourage users to contribute Forums • Support by users for users • Active community - 10s-100s of posts/week • Incubating the 10G mailing-list into a forum

  16. International Community Over 1,000 users, using 2,000 cards at 150 universities in 40 countries

  17. NetFPGA’s Defining Characteristics • Line-Rate • Processes back-to-back packets • Without dropping packets • At full rate of 10 Gigabit Ethernet Links • Operating on packet headers • For switching, routing, and firewall rules • And packet payloads • For content processing and intrusion prevention • Open-source Hardware • Similar to open-source software • Full source code available • BSD-Style License for 1G and LGPL 2.1 for 10G • But harder, because • Hardware modules must meeting timing • Verilog & VHDL Components have more complex interfaces • Hardware designers need high confidence in specification of modules

  18. Test-Driven Design • Regression tests • Have repeatable results • Define the supported features • Provide clear expectation on functionality • Example: Internet Router • Drops packets with bad IP checksum • Performs Longest Prefix Matching on destination address • Forwards IPv4 packets of length 64-1500 bytes • Generates ICMP message for packets with TTL <= 1 • Defines how packets with IP options or non IPv4 … and dozens more … Every feature is defined by a regression test

  19. Who, How, Why Who uses the NetFPGA? • Teachers • Students • Researchers How do they use the NetFPGA? • To run the Router Kit • To build modular reference designs • IPv4 router • 4-port NIC • Ethernet switch, … Why do they use the NetFPGA? • To measure performance of Internet systems • To prototype new networking systems

  20. Spring Camp Objectives • Overall picture of NetFPGA • How reference designs work • How you can work on a project • NetFPGA Design Flow • Directory Structure, library modules and projects • How to utilize contributed projects • Interface/Registers • How to verify a design (Simulation and Regression Tests) • Things to do when you get stuck AND… You can build your own projects!

  21. Section II: Network review

  22. Internet Protocol (IP) Data to be transmitted: Data … IP packets: IP Hdr IP Hdr IP Hdr Data Data Data … Ethernet Frames: Eth Hdr Eth Hdr Eth Hdr IP Hdr IP Hdr IP Hdr Data Data Data

  23. Internet Protocol (IP) Data … 1 4 16 32 Ver HLen T.Service Total Packet Length Fragment ID Flags Fragment Offset IP Hdr Data 20 bytes TTL Protocol Header Checksum Source Address Destination Address Options (if any)

  24. Basic operation of an IP router D R3 R1 R4 D A B E R2 C R5 Destination Next Hop F D R3 E R3 F R5

  25. Basic operation of an IP router R3 R1 R4 D A B E R2 C R5 F

  26. Forwarding tables 32 bits wide → ~ 4 billion unique address IP address Naïve approach: One entry per address ~ 4 billion entries Improved approach: Group entries to reduce table size

  27. IP addresses as a line Your computer My computer Stanford Berkeley Asia North America 0 232-1 All IP addresses

  28. Longest Prefix Match (LPM) Universities Continents Planet To: Stanford Data • Matching entries: • Stanford • North America • Everywhere Most specific

  29. Longest Prefix Match (LPM) Universities Continents Planet To: Canada Data • Matching entries: • North America • Everywhere Most specific

  30. Implementing Longest Prefix Match Searching Most specific FOUND Least specific

  31. Basic components of an IP router Management & CLI Routing Protocols Software Control Plane Routing Table Data Plane per-packet processing Forwarding Table Switching Queuing Hardware

  32. IP router components in NetFPGA Linux SCONE Management & CLI Management & CLI Routing Protocols OR Software Routing Protocols Routing Table Routing Table Router Kit Output Port Lookup Input Arbiter Output Queues Hardware Forwarding Table Switching Queuing

  33. Section III: Example I

  34. Operational IPv4 router Java GUI SCONE Management & CLI Control Plane Software Routing Protocols Routing Table Reference router Forwarding Table Switching Queuing Data Plane per-packet processing Hardware

  35. Streaming video

  36. Streaming video NetFPGA running reference router PC & NetFPGA (NetFPGA in PC)

  37. Streaming video Video streaming over shortest path Video client Video server

  38. Streaming video Video client Video server

  39. Observing the routing tables • Columns: • Subnet address • Subnet mask • Next hop IP • Output ports

  40. Example 1

  41. Review NetFPGA as IPv4 router: • Reference hardware + SCONE software • Routing protocol discovers topology Demo: • Ring topology • Traffic flows over shortest path • Broken link: automatically route around failure

  42. Section III: Example II

  43. Buffers in Routers Rx Rx Rx Tx Tx Tx • Internal Contention • Pipelining • Congestion

  44. Buffer Sizing Story

  45. Using NetFPGA to explore buffer size • Need to reduce buffer size and measure occupancy • Alas, not possible in commercial routers • So, we will use the NetFPGA instead Objective: • Use the NetFPGA to understand how large a buffer we need for a single TCP flow.

  46. Reference Router Pipeline CPU RxQ MAC RxQ CPU RxQ MAC RxQ CPU RxQ MAC RxQ CPU RxQ Output Queues MAC RxQ MAC TxQ CPU TxQ MAC TxQ CPU TxQ MAC TxQ CPU TxQ MAC TxQ CPU TxQ Input Arbiter Output Port Lookup • Five stages • Input interfaces • Input arbitration • Routing decision and packet modification • Output queuing • Output interfaces • Packet-based module interface • Pluggable design

  47. Extending the Reference Pipeline MAC RxQ CPU RxQ MAC RxQ CPU RxQ MAC RxQ CPU RxQ MAC RxQ CPU RxQ Input Arbiter Output Port Lookup Event Capture Output Queues MAC TxQ CPU TxQ Rate Limiter CPU TxQ MAC TxQ CPU TxQ MAC TxQ CPU TxQ MAC TxQ

  48. Enhanced Router Pipeline MAC TxQ MAC RxQ Output Queues MAC RxQ CPU RxQ MAC RxQ CPU RxQ CPU RxQ MAC RxQ CPU TxQ CPU TxQ Rate Limiter MAC TxQ CPU TxQ MAC TxQ CPU TxQ MAC TxQ CPU RxQ Event Capture Output Port Lookup Input Arbiter Two modules added • Event Capture to capture output queue events (writes, reads, drops) • Rate Limiter to create a bottleneck

  49. Topology for Exercise 2 Recall: NetFPGA host PC is life-support: power & control So: The host PC may physically route its traffic through the local NetFPGA NetFPGA running extended reference router nf2c2 nf2c1 eth2 PC & NetFPGA (NetFPGA in PC) eth1 Iperf Client IperfServer

  50. Example 2

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