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Predictable Design of Embedded Systems using Networked Architectures

Predictable Design of Embedded Systems using Networked Architectures. Henk Corporaal www.ics.ele.tue.nl/~heco ASCI Winterschool on Embedded Systems Rockanje, March 2006. Outline. Trends and design problems Unpredictability Platforms Predictable design Proposed design flow Open issues

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Predictable Design of Embedded Systems using Networked Architectures

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  1. Predictable Designof Embedded SystemsusingNetworked Architectures Henk Corporaal www.ics.ele.tue.nl/~heco ASCI Winterschool on Embedded Systems Rockanje, March 2006

  2. Outline • Trends and design problems • Unpredictability • Platforms • Predictable design • Proposed design flow • Open issues Note: this lecture is not about a solved problem Henk Corporaal

  3. Outline • Trends and design problems • Embedded systems everywhere • Design practice • Design complexity • Memory wall • Unpredictability • Platforms • Predictable design • Design flow • Open issues Henk Corporaal

  4. Embedded systems everywhere • Convergence of 3 Cs computers, communications and consumer electronics • The computer enters the 3rd fase computing power - networking - intelligent processing • The world is 1 network wherever, whenever, all information and communication available We get a smart environment Henk Corporaal

  5. Design practice: Informal system specification System people Task Task Task Paper spec vhdl C verilog ASM Hardware people Software people Integration Henk Corporaal

  6. Design practice Structure description System Behavioral specification Algorithm R/T Logic circuit Y-Chart (Gajski-Kuhn) • Design Flow is path in Y chart • Till RT-level largely manual flow Physical realization Henk Corporaal

  7. Design complexity problem complexity Process technology + 58% 103 HW gap 102 HW design productivity +21 % SW gap 101 SW productivity + 8 % 4 8 12 16 year Henk Corporaal

  8. Hitting the memory wall Processor-Memory Performance Gap:(grows 50% / year) Performance µProc: 55%/year 1000 CPU 100 “Moore’s Law” 10 DRAM: 7%/year DRAM 1 2005 1980 1985 1990 1995 2000 Time [Patterson] Henk Corporaal

  9. Outline • Trends and design problems • Unpredictability • Platforms • Predictable design • Proposed design flow • Open issues Henk Corporaal

  10. Unpredictability at all levels Uncertainty increases at all levels applications architectures DSM VLSI design Henk Corporaal

  11. resources mem Txt gen mem HSRC VSRC Video In1 NR HSRC VSRC Video In2 NR HSRC VSRC mix 100Hz Peak Matrix mix mem time Application: Two forms of unpredictability • Applications can be data dependent • Applications may have different scenarios Henk Corporaal

  12. In addition: dynamic changing set of applications 125 SCH = SCH search Inter-system handover SCH SCH 100 SCH SCH CPICH search Compute load  75 SCH SCH CPICH search RAKE chip-rate processing CPICH search 50 RAKE chip-rate processing CPICH search WLAN receiver 25 SCH RAKE sym-rate proc. RAKE sym-rate proc. WLAN acquisition time UMTS connected UMTS connected/ WLAN acquisition WLAN connected/ UMTS monitoring Initial acquisition Multi-standard modem operation • Several applications have to be activated simultaneously • Too many combinations for an analysis at design time (non deterministic events) [Philips EVP] Henk Corporaal

  13. Architecture unpredictability cpu cpu $ $ IP IP IP IP IP IP IP IP IP IP IP IP IP IP IP IP ext. mem Local schedulers: • OS • task switching • interrupts • cache strategy • cache pollution • interconnect • busses, bridges • networks • memory controllers • external memory e.g. RR, TDMA, FCFS, LRU, EDLF, FIFO, priority, … mem arb. interconnect interconnect interconnect … … … … What is the global behavior (end-to-end), composed of interacting local solutions ? Henk Corporaal

  14. DSM VLSI Unpredictability • Global wiring delay becomes dominant over gate delay (timing closure) Henk Corporaal

  15. DSM VLSI Unpredictability Length of Isosynchronous zone as function of frequency Other DSM problems: • Clock distribution, skew • VDD and VSS voltage drop • Signal integrity, cross-talk • Variance in process parameters increases Henk Corporaal

  16. Unpredictability: Design Closure problems Design closure = • a realization meets all requirements, including functionality, speed, power, area, yield, etc., without design iterations application mapping & scheduling architecture placement & routing Closure problem at all levels FPGA realization VLSI realization Henk Corporaal

  17. Unpredictability: Design Closure problems 1200% 1000% 800% 600% 400% 200% 0% Computational Requirements → Orders of Magnitude Time → Mapping with performance guarantees looks impossible !! Henk Corporaal

  18. Solution ingredients: • Higher abstraction levels • SW and HW IP reuse / PnP principle • Standards • Avoid large design iterations • Design correct by synthesis • Avoid worst case resource requirements How do we achieve all of this? Henk Corporaal

  19. Outline • Trends and design problems • Unpredictability • Platforms • Predictable design • Design flow • Open issues Henk Corporaal

  20. What is a platform? Definition: A platform is a generic, but domain specific information processing (sub-)system • Generic means that it is flexible, containing programmable component(s). • Platforms are meant to quickly realize your next system • (in a certain domain). • Single chip? Henk Corporaal

  21. Platforms, why? • Reuse • Short Time-to-Market • High Quality • Flexible and Programmable • Large software component • Standardization • Optimized for specific domain • and you do not have to solve this design closure problem !! Henk Corporaal

  22. Platforms separate the design communities ! Applications SDT system design technology Design technology Platform PDT platform design technology Enabling technologies Henk Corporaal

  23. Platform examples: Digital camera Sanyo [Okada99] Henk Corporaal

  24. TI OMAP 192Kbyte shared SRAM 8Kb data cache (2-way, 512 lines of 16 bytes) Write buffer (17 elements) 16Kb (2-way) 16Kb (2-way) 8Kb mem (2x 4K) 64Kb dual port (8x 4K x 16b) 96Kb single port (12x 4k x 16b) 32Kb ROM Up to 192Mbyte off-chip memory Henk Corporaal

  25. SpaceCake (Philips research) • Homogeneous: set of equal tiles • Per tile e.g.: • n * MIPS • m * TriMedia • Accelerators • k * L2 Cache bank • Shared memory • Cache coherency • Big interconnect switch • Inter Tile: • Router • Message passing • Working on inter tile cache coherence switch L2 cache memory banks Single tile Henk Corporaal

  26. IMAGINE Stream Processor (Stanford) • IMAGINE = SIMD of VLIWs • It is controlled by a host processor, which send it stream instructions (Load, store, receive, send, VLIW op, load microcode) Henk Corporaal

  27. Hybrid FPGAs: Xilinx Virtex 4-Pro GHz IO: Up to 16 serial transceivers PowerPC Memory blocks & Multipliers PowerPCs ReConfig. logic Reconfigurable logic blocks Courtesy of Xilinx (Virtex II Pro) Henk Corporaal

  28. Fundamental platform design decisions • Homogeneous versus Heterogeneous ? • Bus versus Network ? • Shared memory versus Message passing ? • QoS support, Guarantees built-in ? • Generic versus Application specific ? • What types of parallelism to support ? • ILP, DLP, TLP • Focus on Performance, Power or Cost ? • Memory organisation ? • HW or SW reconfigurable ? And further: • OS support, Middleware ? • Mapping support? Henk Corporaal

  29. Homogeneous or Heterogeneous • Homogenous: • replication effect • memory dominated any way • solve realization issuesonce and for all • less flexible Henk Corporaal

  30. Homogeneous or Heterogeneous • Heterogeneous • more flexible • better fit to application domain • smaller increments • no tile reuse Henk Corporaal

  31. Homogeneous or Heterogeneous • Middle of the road approach • Flexibile tiles • Fixed tile structure at top level tile router Henk Corporaal

  32. HW or SW reconfigurable? Spatial mapping FPGA Temporal mapping VLIW configuration bandwidth reset Reconfiguration time loopbuffer context Subword parallelism 1 cycle fine coarse Data path granularity Henk Corporaal

  33. Outline • Trends and design problems • Unpredictability • Platforms • Predictable design • Current practise • Predictability • Architecture consequences • Design consequences • Design flow • Open issues Henk Corporaal

  34. How should we design ? • Trajectory, from Idea to Realization • Desicions based on models • Abstract from implementation details (not all known yet) • Relatively cheap to create, validate and simulate Idea Design Time Concepts Requirements Design Problem • Generate Ideas • Construct Models • Evaluate Properties • Make Design Decisions “Steers” Realization Henk Corporaal

  35. Current practiceMapping, easy, but........... Idea • Given • reference C code for applicatione.g. MPEG-4 Motion Estimation • platform: SUPERDUPER-LX50 • Task • map application on architecture • But … wait a moment me@work> CC –o2 mpeg4_me mpeg4_me.cThank you for running SUPERDUPER-LX50 compiler.Your program uses 257321886 bytes memory, 78 Watt, 428798765291 clock cycles a=b*5+d; for (...) {.. } Henk Corporaal

  36. Post analysis: check constraints after mapping Simulation based Does it still work for other data ? Does it still work when other applications are active ? Too many iterations Easy to program, hard to tune Can this be improved ? e.g. Constraints = input Current design process application mapping constraints OK ? no yes Henk Corporaal

  37. Predictable design What is it? • Being able to reason at a high level about a design (in terms of functional and non-functional properties) and • Being able to realize this design without time consuming iterations in the design flow (design closure) How: • Predictable architecture • Making resources predictable • Proper modeling of less predictable elements • Predictable design flow • Compositionality • Composability • Design time analysis  Run time analysis Henk Corporaal

  38. Making architectures predictable • Getting rid of all unpredictable elements • Caches ? • No problem, but WCET estimation may be big and unacceptable ! • Software controlled • locked cache lines • non-cachable memory • controlled replacement • Shared memory • Communication Henk Corporaal

  39. Making architectures predictable: NoC Philips AETHEREAL R R R R R R R R R Router provides both guaranteed throughput (GT) and best effort (BE) services to communicate with IPs. Combination of GT and BE leads to efficient use of bandwidth and simple programming model. Router Network Network Interface IP Network Interface Network Interface IP IP Henk Corporaal

  40. Making the NoC predictable: how to support GT traffic? Time wheel concept • control injection traffic at network interface time 1 8 2 7 3 6 5 4 Henk Corporaal

  41. Making the design flow predictable : Compositionality b y a High level design x z P(x,y) if [P(a,b),...] ! b y a Low level design x z P(x,y) if [P(a,b),...] ? Henk Corporaal

  42. Making the design flow predictable Freq Sc1 Sc2 Sc3 Load • Design time • Determine of upper bounds on time and resources pareto curves • Scenario discovery: • separate your application in parts for which upper bounds not too far from worst case Henk Corporaal

  43. What do we want ? Design time analysis Example: • Given • Comp. Resources • Bandwidth • Buffer size • Throughput •  Pareto curve A5 A4 A1 A2 A3 P1 P2 P3 P4 1/Throughput (q1,c1) Cost (resources) Single application • Reasoning about end-to-end timing constraints (for given resources and quality) = predictability • Which local arbitration mechanisms are needed ? • How to translate this to the global level ? Henk Corporaal

  44. Scenarios: MP3 Henk Corporaal

  45. What do we want ? Composability A1 A2 Proc1 Proc2 A3 A4 • Multiple applications • If app. 1 and app. 2 fit each individually, what can be said about the combination ? • Concept of virtual platform Henk Corporaal

  46. Predictability: ComposabilityCan we add Pareto points? application 1 application 2 Q Q (q1,c1) (q2,c2) Cost (resources) Cost (resources) + (q1+q2,c1+c2) ? Henk Corporaal

  47. Problem: Predictable Resource utilization? Mapping & Scheduling P1 P2 P3 50 50 50 50 A B 50 50 Henk Corporaal

  48. Problem – Predictable Resource utilization? 50 50 50 50 A B 50 50 P1 A P2 B P3 t t t t 1 0 2 3 Scheduling conflict! Add ordering dependences (edges) Only 50% processor utilization ! Henk Corporaal

  49. Where is the problem? • Different throughput obtained for different order of actors • Possibilities of overall graph increases exponentially with number of actors and individual graphs • Very difficult to do a complete analysis to obtain an optimal order • Hard to model and analyze different arbitration strategies realistically Henk Corporaal

  50. Problem – Too many possibilities! A B C Henk Corporaal

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