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2014 Spring ASIC /SOC Design. A Top-down Design Methodology with Embedded Aging Sensors for Robust System Design. Xinfei Guo 5/9/2014. Outline. Motivation Aging sensor cell Top-down design methodology Future work. Aging/ Wearout. Reliability: time dependent degradation
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2014 Spring ASIC/SOC Design A Top-down Design Methodology with Embedded Aging Sensors for Robust System Design Xinfei Guo 5/9/2014
Outline • Motivation • Aging sensor cell • Top-down design methodology • Future work
Aging/Wearout • Reliability: time dependent degradation • Device level: parametric shift over time (e.g.Vth,u) • Circuit and architecture level • Irreversible and reversible(e.g. BTI) [M. Alamet al. Microelectronics Reliability ’07]
Bias Temperature Instability(BTI) • Trapping/Detrapping[J. Velamala et al. DAC’12] • Get worse and worse • Both NBTI and PBTI • Stress and Recovery [M. Lee et al. ASP-DAC ’11]
Why Aging Sensor? • Track and monitor aging • Adaptive circuit tuning (e.g. DVFS) • “Check engine light” for recovery techniques
Related Work • Ring Oscillator based “Silicon Odometer” [T. Kim et al. VLSI ’07, JSSC ’08] - Area overhead, complex, process variation • Metastable element based [A. Cabe et al. ISQED ’09][S. Wooters, et al. TVLSI ’12] - Small and embedded - Good time resolution - Distributed
Sensor Cell Set the margin Design the sensor Check the engine Source: S. Wooters, et al. TVLSI ’12
Why Top-Down Design? • Top-down design for sensor itself - Reduce design time - Reduce impact of process variations - Designware cell • Top-down design with sensor embedded - Different behavior of each block - Different Thermal Behavior - Distributed with Smaller area overhead
Sensor Cell • Instantiate the library cell
Scan chain cell – Read Output Scan cell New Scan Cell
New ScanCell Flow agingsensor.v Design Compiler Std cell lib Scancell agingsensor_dc.v IC Compiler newscancell.v agingsensor.CEL agingsensor.FRAM IC Compiler Design Compiler newscancell_dc.v newscancell.CEL newscancell.FRAM
Top-down design with aging sensor embedded Basic DC Synthesis(Design Compiler) Basic Scan Synthesis Flow (Design For Test Compiler) Update the netlist Add to Reference Library (New scan cell library)
Case Study: Johnson Counter … n=total # of SDFF; t=user defined parameter; # application dependent for(i=0;i<=n;i+t) {Replace the SDFFARX1 with sensorSDFFX1; Add global control signals; D=deg_in; } …
Case Study: Johnson Counter t=2 t=1
Future work • Verification • Tradeoff between # of sensor vs. accuracy • Placement of the sensor • Both NBTI and PBTI • Optimize area • Trigger recovery • Silicon Validation
Thanks! • Q & A