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Advanced DEPFET Sensor Technology for LC Vertex Detector

Discover the operational principles, design, and advantages of DEPFET sensors in LC vertex detectors. Learn about the technology, pre-tests, simulation, and pixel prototypes. Explore the low-noise, high-sensitivity capabilities and innovative features of DEPFET sensors. Key topics include wafer thinning, self-aligning technology, production processes, and imaging spectroscopy applications with pixel details. Stay informed about the cutting-edge advancements in DEPFET technology.

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Advanced DEPFET Sensor Technology for LC Vertex Detector

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  1. DEPFET sensors for a LC vertex detector (1) L. Andriceka, P. Fischerb, K. Heinzingera, P. Lechnera, G. Lutza, I. Pericb, M. Reichec, R.H. Richtera, G. Schallera, M. Schneckea, F. Schoppera, H. Soltaua, L. Strüdera, J. Treisa, M. Trimplb, J. Ulricib, N. Wermesb aMPI Halbleiterlabor Munich bUniv. of Bonn cMPI für Mikrostrukturphysik Halle, Germany • DEP(leted)F(ield)E(ffect)T(ransistor) operation principles • Results of pre-tests • DEPFET prototype run • Technology, simulation and design • Wafer thinning • Concept, first results • Summary R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  2. Radiation ~1mm - - - + - + - + + - DEPFET-Prinziple ~300 mm FET integrated on high ohmic n-bulk Collection of electrons within the internal gate Modulation of the FET current by the signal charge! Advantages: Amplification of the charge at the position of collection => no transfer loss Full bulk sensitivity Non structured thin entrance window (backside) Very low input capacitance => very low noise R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  3. Excellent noise values measured on single pixels 55Fe-spectra @ 300K ENC = 4.8 +/- 0.1 e- R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  4. BioScope - imaging of tracer-marked bio-medical samples (P. Klein and W. Neeser) Noise: ca. 70 ENC @ 300K Slow operation (old technology) Large arrays are impossible (JFET => VP variations) Large cell size

  5. Rectangular DEPFET pixel detector MOS transistor instead of JFET A pixel size of ca. 20 x 20 µm² is achievable using 3µm minimum feature size. R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  6. DEPFET pixel matrix Low power consumption Fast random access to specific array regions • Read filled cells of a row • Clear the internal gates • of the row • - Read empty cells R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  7. DEPFET Technology Double poly / double aluminum process on high ohmic n- substrate perpendicular to channel (with clear) along p-channel R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  8. Self aligning Technology Positions of all essential implantations are determined not by masks but by polysilicon layers shallow channel implantation • mandatory for rectangular cells • (lateral channel definition) • - reduces parameter variations • on the wafer R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  9. Technology – pre-tests • Motivation • Low leakage current <-> new technology • First MOS transistor parameters for the DEPFET and readout electronics design • Process know how and design rules Pre-tests: Device test: Single poly, single Al, MOS technology on 300µm silicon + Numereous deposition, lithography and etching tests R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  10. Pre-test diodes Reference diodes IBulk =100pA/cm2 IBulk =100pA/cm2 Pretest results: Diode leakage currents R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  11. Linear MOS Transistors (self aligned technolgy) L=5µm L=7µm VGS = -4V...-7V @VB=10V R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  12. Pixel prototype production (6“ wafer)for XEUS and LC (TESLA) Aim: Select design options for an optimized array operation (no charge loss, high gain, low noise, good clear operation) On base of these results => production of full size sensors Many test arrays - Circular and linear DEPFETS up to 128 x 128 pixels minimum pixel size about 30 x 30 µm² - variety of special test structures Production will be finished in spring R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  13. imaging spectroscopy 7.68 x 7.68 cm² 1024 x 1024 pixels 1 Mpix 75 µm 300 ... 500 µm 4 el. ENC 1.2 msec 2.5 µsec purpose detector format pixel size thickness noise readout time / detector / row particle tracking 1.3 x 10 cm² (x 8) 520 x 4000 pixels (x 8) 2.1 Mpix (x8) 25 µm 50 µm ~ 100 el. ENC 50 µsec 20 nsec

  14. Active Pixel Sensor (rectangular) • 2 pixels • 30 x 30 µm² • DEPFET • L = 5 µm • W = 18 µm • reduce the required read out speed by 2 doubles the number of read out channels

  15. Depth 10µm Depth 7µm Depth 4µm Depth 1µm External (internal) Gates Sources n+ clear contacts Drain Cell size 36 x 27 µm² Potential during collection - 3D Poisson equation (Poseidon) (50µm thick Si, NB=1013cm-3,VBack=-20V) R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  16. Depth 1µm Hiding the n+-clear contacts The positive Clear pulse removes the electrons from the Internal Gate and also pushs the holes out of the deep p cover region. After returning of the clear the deep p remains negatively charges forming a shield for the signal electrons. R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  17. Potential distribution during Reading 2D dynamic simulation along the channel ID adjusted to 100µA (W/L =18µm/5µm) Vinternal Gate ca. 3V Localized charge generation simulates a hit Back contact Internal Gate Source Drain R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  18. DEPFET simulation – TeSCA (2D, time dependent) hit response to a generation of 1600 electron-hole pairs

  19. Poseidon (3D Poisson equ.) Includes 3D effects => VClear=20V Simulation of the Clear mechanism TeSCA (2D, time dependent) Removal of 1600 electrons from the internal gate (VClear=15V)

  20. Current production statusPixel array section – Design with clockable clear gate 1 Pixel cell • N-side view with two polysilicon layers and contact openings • To do: • - P-side processing • - Metallization Drain Gate Clear Clear gate Source R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  21. Processing thin detectors- the Idea - R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  22. Detector thinning – first results Thickness of detector region : 50µm of frame : 350µm Size: 8cm x 1cm Wafer bonding – MPI f. Festkörperstrukturphysik, Halle Wafer grinding – SICO GmbH, Jena Anisotropic etching – CiS gGmbH Erfurt, MPI Halbleiterlabor Munich R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  23. Summary • DEPFET is promising detector candidatefor future HE and astrophysics experiments. Key features: low noise, full bulk sensitivity, no charge transfer loss, low power consumption, random access within an array • A new DEPFET technology (2 poly/ 2 aluminum) was developed for large arrays and high speed operation • A DEPFET Prototype production has been started with DEPFET arrays with • 30 x 30 µm² pixel size (TESLA) to 75 x 75 µm² XEUS • - Technology and device simulations are looking encouraging • - Technological pre-tests show very good electrical parameters • (leakage currents and MOS transistor characteristics) • A concept for merging the DEPFET technology with a thinning technology is proposed • - thin mechanical detector samples were fabricated • First wafers will be finished in spring ‘03 R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

  24. Processing thin detectors- Wafer bonding - 10 “SOI” Wafer prepared by MPI für Microstrukturphysik, Halle ≈1 cm/sec Q.-Y. Tong and U. Gösele “ Semiconductor Wafer Bonding ” John Wiley & Sons, Inc. picture from: www.mpi-halle.mpg.de R. H. Richter et al - VERTEX 2002 Kailua-Kona, 05.11.2002

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