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Monolithic Active Pixel Sensors for the TESLA Vertex Detector

Monolithic Active Pixel Sensors for the TESLA Vertex Detector. - Student Seminar, 13 June 2003 -. Devis Contarato University of Hamburg. Outline. Introduction: TESLA requirements Principles of operation of MAPS Activities of the DESY/Uni-HH group Charge collection simulations

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Monolithic Active Pixel Sensors for the TESLA Vertex Detector

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  1. Monolithic Active Pixel Sensors for the TESLA Vertex Detector - Student Seminar, 13 June 2003 - Devis Contarato University of Hamburg

  2. Outline • Introduction: TESLA requirements • Principles of operation of MAPS • Activities of the DESY/Uni-HH group • Charge collection simulations • Test-stand measurements • Conclusions D. Contarato STUDENT SEMINAR - 13 June 2003

  3. B=4 T Introduction: requirements of TESLA VXD • High impact parameter resolution • spatial resolution<5 m • multiple scattering<0.1% X0 • thin layers ~50 m • High granularity (high jets multiplicity) • pixel pitch of ~20x20 m2 • High occupancy (e+e- pairs background) • fast read-out • on-line data sparsification The technology needs to combine high granularity, little multiple scattering, high read-out speed and radiation hardness: • Harsh radiation environment: • neutron5·109 n(1 MeV)/cm2/5 years • Dionisation= 100 kRad/5 years Pixel detectors D. Contarato STUDENT SEMINAR - 13 June 2003

  4. Technological options for the TESLA VXD • Charge Coupled Devices (CCD) • Active Pixel Sensor (APS) • - Hybrid Active Pixel Sensors (HAPS) • (present day technology for pixel detectors in HEP) • - Monolithic Active Pixel Sensors (MAPS) • (the technology for future LC?) D. Contarato STUDENT SEMINAR - 13 June 2003

  5. Charge Coupled Devices (CCDs) • thin detectors • charge is transferred through the bulk (radiation hardness?) • column-parallel read-out (to improve the limited read-out speed) • low power dissipation D. Contarato STUDENT SEMINAR - 13 June 2003

  6. chip sensor Hybrid Pixels • The read-out chip is mounted directly on top of the pixels (bump-bonding) • Each pixel has its own read-out amplifier • Fast read-out and rad-hard • … but: • Pixel area limited by the size of the read-out chip • High material budget and high power dissipation D. Contarato STUDENT SEMINAR - 13 June 2003

  7. Principle of operation of MAPS 15 µm • double-well CMOS process with epitaxial layer • the charge generated by the impinging particle is reflected by the potential barriers due to doping differences and collected by thermal diffusion by the n-well/p-epi diode • 100% fill factor • integration of the circuitry electronics on the same sensor substrate Reset Collection Output Reset… D. Contarato STUDENT SEMINAR - 13 June 2003

  8. MAPS: a technology for the TESLA VXD? • CCDs • thin (low material budget), good granularity • low read-out speed and neutron radiation tolerance to be proved • Hybrid pixels • fast and (presumably) more radiation-hardened thick (high material budget), poor granularity • MAPSseem to combine the positive features of both: • high granularity and possibility ofthinning down • improved read-out speed • radiation tolerance • use of a standard and cheap CMOS technology D. Contarato STUDENT SEMINAR - 13 June 2003

  9. First prototypes: MIMOSA I – II MIMOSA = Minimum Ionising MOSActive pixel sensor MIMOSA I: technology demonstration • standard 0.6mm CMOSof AMS • 14m thick EPI layer (1014cm-3) • pixel pitch 20x20 m2 • 4 arrays 64x64 pixels • analogue readout - max. clock freq.: 5MHz die size 3.6x4.2mm2 MIMOSA II: noise and radiation tolerance studies (use of different pixel layouts) • standard 0.35mm CMOS of MIETEC • 4.2 mthick EPI layer (1015cm-3) • pixel pitch 20x20 m2 • 6 arrays 64x64 pixels; • radiation toleranttransistor design • analogue readout - max. clock freq.: 25MHz die size 4.9x3.5 mm2 D. Contarato STUDENT SEMINAR - 13 June 2003

  10. 128x128 APS array max 40 MHz readout test APS arrays First prototypes : MIMOSA III – IV MIMOSA III: trial of a deep-submicronic process • standard 0.25 mCMOS of IBM • 2.5 m thick EPI layer(~1015 cm-3) • pixel pitch 8x8 m2 • 2 arrays 128x128 pixels • analogue readout - max. clock freq. 40 MHz die size 4.0x2.0 mm2 MIMOSA IV: study of substrate contribution and of new charge sensing elements • standard 0.35 m CMOS of AMS • p-substrate process(~1014cm-3): no EPI layer • pixel pitch 20x20 m2 • 4 arrays 64x64 pixels • radiation tolerant transistor design • analogue readout - max. clock freq.40 MHz die size 3.7x3.8 mm2 D. Contarato STUDENT SEMINAR - 13 June 2003

  11. MIMOSA V: first real-size prototype chip size 1.73x1.73 cm2 Wafer view • standard 0.6mm CMOS of AMSwith 14m thick EPI layer(1014cm-3) • pixel pitch17x17m2 • 4 independent matrices of 510x512 pixels read-out in parallel • first real size prototype: 3.5 cm2, 1M pixels • serial analogue readout - max. clock freq.: 40 MHz • back-thinning down to 120 mm • coarse stitching (~100 mm) D. Contarato STUDENT SEMINAR - 13 June 2003

  12. Achievements of first MAPS prototypes (Ires-Lepsi, Strasbourg,France) • Good and promising tracking performances of the small-scale prototypes: ~99%,sp~1.5-2.5 m, S/N~30. • Preliminary results with MIMOSA V show that these performances are reproducible with real-size detectors (…BUT: problems connected with large area chips: yield, noise) • Tolerance to neutrons exceeds TESLA requirements (…BUT:degradation after ionizing radiation, not understood) • Technology without EPI-layer (MIMOSA IV) has also shown good perfomances (…BUT: poorer resolution due to larger charge spread) • R&D collaboration started from Strasbourg and joined by several centers in Europe (F-D-CH-NL) D. Contarato STUDENT SEMINAR - 13 June 2003

  13. DESY/Uni-HH activities on MAPS • Detector performance and radiation damage studies • Simulation of charge collection (ISE-TCAD) • Test-stand and test-beam measurements (MIMOSA V) • Radiation damage and material investigations • Mechanical design and cooling • Mechanics: CAD design of VXD layers layout • VXD cooling: simulations, material budget, power switching • General detector design and optimization • - Physics simulation of Vertex Detector D. Contarato STUDENT SEMINAR - 13 June 2003

  14. Issues for device simulation (ISE-TCAD) • 3-D device physics simulations are performed in order to: • understand the charge collection mechanism and its time properties • estimation of the charge collection efficiency • study of the spatial charge spreading onto neighboring pixels • study of theinfluence of technological parameterson the sensor charge collection properties • optimisation of the sensor design D. Contarato STUDENT SEMINAR - 13 June 2003

  15. Boundaries… Doping… Mesh… Physics… Parameters… Solve… + Description of boundaries, doping and mesh Overview of ISE-TCAD simulations MESH GENERATOR Physical models and parameters DEVICE PHYSICS SIMULATOR SIMULATION RESULTS VISUALISATION TOOLS D. Contarato STUDENT SEMINAR - 13 June 2003

  16. Particle track • Simulated structure: 3-dim model of 3x3 pixel cluster (3 pixels in 2-dim) • Technological details and doping profiles from foundry (approximate) • The passage of a MIP is simulated introducing an excess charge (80 e-h pairs/µm) • Transient simulation: relaxation process of achieving equilibrium after the particle passage • Study of different impact positions for the simulated MIP Simulation of charge collection 0 nsec 1 nsec 10 nsec 20 nsec D. Contarato STUDENT SEMINAR - 13 June 2003

  17. MIMOSA V Simulation Central hits particle track Pixel pitch 17 mm, diode 3 mm, EPI-thickness 14 mm, 3x3 pixels cluster • larger diffusion in the epilayer, fast recombination in the substrate (different carrier lifetimes) • expected signal ~1100 e: large charge sharing (clustering) • charge collection times <100 ns • ratio Qsingle/Q3x3~60% agrees well with measurements D. Contarato STUDENT SEMINAR - 13 June 2003

  18. Going to deep-submicron technology Configuration of the collecting diode in a sub-m process with Shallow Trench Isolation Example of simulated structure and geometrical parameters used in the simulations • Future: probably only deep-submicron technology available • smaller epilayer thickness (smaller signal) • latch-up of the transistors requires trench isolation • radiation-induced interface states at the Si/SiO2 interface • substrate contribution to the collected charge D. Contarato STUDENT SEMINAR - 13 June 2003

  19. Charge collection in deep-submicron MAPS Pixel pitch 20 mm, diode 1 mm, EPI-thickness 28 mm, typical doping profiles Mean • Linear dependence of collected signal on epilayer thickness • Important substrate contribution • A thinner epilayer results in smaller signal, butlimited charge spreadingand shorter collection times(faster collection) D. Contarato STUDENT SEMINAR - 13 June 2003

  20. Simulation of interface damage No shallow trench isolation Shallow trench isolation Epi 8 µm (Interface traps concentrations: 1011, 1012 1/eVcm2~500 krad, Wüstenfeld 2001, Ph.D. thesis) • Significant dependence of the collected charge on the trench geometry (mainly on depth, less dependence on trench width) • Collection times are not affected • How to overcome the problem: PolySi instead of Si02? D. Contarato STUDENT SEMINAR - 13 June 2003

  21. Test stand • MIMOSA V chip(256K pixels/matrix) • clocked with 10 MHz • chip read-out 26ms • Cooling unit • VME-Based readout • - clock & reset signals • - ADC board • Source tests • 55 Fe - X ray, 106 Ru - electrons • Planned tests: • Test-beam • IR laser light injection • Temp. and B-field dependence • on/off power switching D. Contarato STUDENT SEMINAR - 13 June 2003

  22. Data acquisition system Interface board -Repeater Cooling block (0oC<T<40oC) Imager board – VME Flash ADC unit Repeater board Chip MIMOSA V chip on front-end board and cooling unit Source Serial analog output VME-based read-out system and hardware data processing units Software for data acquisition and analysis ADC & Imager board Cooler & Thermostat D. Contarato STUDENT SEMINAR - 13 June 2003

  23. Signal processing and Analysis source • Correlated Double Sampling (CDS) on-line: Signal=(Frame2-Frame1) • Analysis: • - central pixel with S/N>10 required • - when found array of 5x5 pixels investigated: neighbors with S/N>2 included in cluster signal • Software for analysis (and DAQ) under development! Fe55 HIT MAP y [pixel] x [pixel] D. Contarato STUDENT SEMINAR - 13 June 2003

  24. Pedestals Pixel pedestal distribution Mean pedestal vs. temperature • T of the coolant and not of the detector is given: there may be a systematic shift • Common-mode noise subtracted • Asymmetrical distribution • Error bars are RMS of the pixel pedestal distribution • Good agreement with fit function: Pedestals ( Ileak ) can be used to measure Ileak after irradiation Leakage current term D. Contarato STUDENT SEMINAR - 13 June 2003

  25. Noise Pixel noise distribution Mean noise vs. temperature T=287 K • Error bars are RMS of the pixel distribution and not the error of the mean • The fit function shows good agreement with the expected behavior: Noise  (Ileak)1/2 Leakage current term D. Contarato STUDENT SEMINAR - 13 June 2003

  26. Calibration with 55Fe 5.9 keV line 6.4 keV line T=287 K • Looking for conversion of the photon in the n-well diode: no charge should appear on the neighbors. • A pixel with S/N>10 is required and NO pixel around it with S/N>1! • 5.9 keV peak used to calibrate the noise:ENC~30-35 • (average pixel noise ~3 ADC counts) • Expected signal from m.i.p. are around 1000 e S/N~30 D. Contarato STUDENT SEMINAR - 13 June 2003

  27. 106Ru - electrons Cluster size distribution Cluster Signal single pixel 3x3 array 5x5 array S/Nneig.=2 Landau fit • S/Ncluster~28(close to that predicted from Fe X-source and noise) • Small difference in most probable signal between 3x3 and 5x5 pixel arrays • Average cluster size ~6 • Spectrum broader than for m.i.p. D. Contarato STUDENT SEMINAR - 13 June 2003

  28. Current developments • Current plans • MAPS with integrated functionalities and on-pixel data processing • New charge-sensing elements: photoFET • Basic radiation studies (test structures) • Exploring fabrication processes (optimum EPI thickness ~8 m) • Goals • Optimisation of detector performances, read-out architecture (CP) and speed (~50 MHz), material and power budget • Fabrication of ladders, improvement of thinning processes • Improvement of radiation tolerance D. Contarato STUDENT SEMINAR - 13 June 2003

  29. MIMOSA VI: integrated data processing AC coupling capacitor Charge storage capacitors Single pixel layout Chip layout • standard 0.35mm CMOS of MIETEC • 4.2 mthick EPI layer(1015cm-3) • pixel pitch 28x28m2 • 1 array 30x128 pixels – 29 transistors/pixel • 24 columns read-out in parallel - max. clock freq.: 30 MHz • Amplification and Correlated Double Sampling on-pixel D. Contarato STUDENT SEMINAR - 13 June 2003

  30. MAPS show good and promising performances for VXD tracking • DESY/Uni-HH group active on chip tests, radiation studies, physics simulation and engineering issues • Full detector simulation tools available • - charge collection simulations • - potential danger of deep-submicron technologies • First results on large-scale prototype • - pedestals and noise resemble leakage current behavior • - cooling is needed to reduce noise • - calibration with 55Fe: ENC~30e -> S/N~30 • - next steps: test-beam studies, irradiations Conclusions D. Contarato STUDENT SEMINAR - 13 June 2003

  31. Open questions • Radiation-tolerance: mechanisms not fully understood. Need for: • test structures for basic studies • device simulations based on measured microscopic parameters • Problems: availability of test structures, lack of technology details • - high energy electrons: might represent an issue? • Mechanics: design of mechanical support in terms of material budget, handling, backthinning • Cooling: power dissipation ~1 kW for the full VXD. Is it possible to switch off between bunch trains?  switch on/off tests • Technological choice for the TESLA VXD not before 2004: will MAPS be ready? D. Contarato STUDENT SEMINAR - 13 June 2003

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