Designing with Verilog

1. Designing with Verilog EECS150 Fall2008 - Lab Lecture #2 Chen Sun Adopted from slides designed by Greg Gibeling EECS150 Lab Lecture #2

2. Today • Lab #1 Solution • Top Down vs. Bottom Up • Partitioning & Interfaces • Behavioral vs. Structural Verilog • Blocking vs. Non-Blocking • Verilog <-> Hardware • Administrative Info • Lab #2 • Primitives EECS150 Lab Lecture #2

3. Lab #1 Solution (1) • The Point • Gets you experience with CAD tools • Simulation • Synthesis • iMPACT • Reinforces Timing • Functional simulation isn’t enough • Simulation != Synthesis • Debugging differences are very difficult EECS150 Lab Lecture #2

4. Lab #1 Solution (2) • Review: • FPGA_TOP2.v • FPGA <-> Board • High level instantiations • Lab1Circuit.v • The accumulator • Two modules • Unusual • Lab1Testbench.v EECS150 Lab Lecture #2

5. Top Down vs. Bottom Up (1) • Top Down Design • Start by defining the project • Then break it down • Starts here: EECS150 Lab Lecture #2

6. Top Down vs. Bottom Up (2) • Top Down Design • Ends here: EECS150 Lab Lecture #2

7. Top Down vs. Bottom Up (3) • Bottom Up Testing • Faster, Easier and Cheaper • Test each little component thoroughly • Allows you to reuse components EECS150 Lab Lecture #2

8. Partitioning & Interfaces (1) • Partitioning • Break the large module up • Decide what sub-modules make sense • Partitioning is for your benefit • It needs to make sense to you • Each module should be: • A reasonable size • Independently testable • Might be built by different people EECS150 Lab Lecture #2

9. Partitioning & Interfaces (2) • Interfaces • A concise definition of signals and timing • Timing is vital, do NOT omit it • Must be clean • Don’t send useless signals across • Bad partitioning might hinder this • An interface is a contract • Lets other people use/reuse your module EECS150 Lab Lecture #2

10. Behavioral vs. Structural (1) • Rule of thumb: • Behavioral doesn’t have sub-components • Structural has sub-components: • Instantiated Modules • Instantiated Gates • Instantiated Primitives • Most modules are mixed • Obviously this is the most flexible EECS150 Lab Lecture #2

11. Behavioral vs. Structural (2) EECS150 Lab Lecture #2

12. Behavioral vs. Structural (3) EECS150 Lab Lecture #2

13. Blocking vs. Non-Blocking (1) Verilog Fragment Result always @ (a) begin b = a; c = b; end C = B = A always @ (posedge Clock) begin b <= a; c <= b; end B = Old A C = Old B EECS150 Lab Lecture #2

14. Blocking vs. Non-Blocking (2) • Use Non-Blocking for FlipFlop Inference • posedge/negedge require Non-Blocking • Else simulation and synthesis wont match • Use ‘#1’ to show causality always @ (posedge Clock) begin b <= #1 a; c <= #1 b; end EECS150 Lab Lecture #2

15. Blocking vs. Non-Blocking (3) • If you use blocking for FlipFlops: YOU WILL NOT GET WHAT YOU WANT! always @ (posedge Clock) begin b = a; // b will go away c = b; // c will be a FlipFlop end // b isn’t needed at all always @ (posedge Clock) begin c = b; // c will be a FlipFlop b = a; // b will be a FlipFlop end EECS150 Lab Lecture #2

16. Blocking vs. Non-Blocking (4) Race Conditions file xyz.v: module XYZ(A, B, Clock); input B, Clock; output A; reg A; always @ (posedge Clock) A = B; endmodule file abc.v: module ABC(B, C, Clock); input C, Clock; output B; reg B; always @ (posedge Clock) B = C; endmodule THIS IS WRONG!! EECS150 Lab Lecture #2

17. Blocking vs. Non-Blocking (5) Race Conditions file xyz.v: module XYZ(A, B, Clock); input B, Clock; output A; reg A; always @ (posedge Clock) A <= B; endmodule file abc.v: module ABC(B, C, Clock); input C, Clock; output B; reg B; always @ (posedge Clock) B <= C; endmodule THIS IS CORRECT!! EECS150 Lab Lecture #2

18. Verilog <-> Hardware (1) assign Sum = A + B; reg [1:0] Sum; always @ (A or B) begin Sum = A + B; end EECS150 Lab Lecture #2

19. Verilog <-> Hardware (2) assign Out = Select ? A : B; reg [1:0] Out; always @ (Select or A or B) begin if (Select) Out = A; else Out = B; end EECS150 Lab Lecture #2

20. Verilog <-> Hardware (3) assign Out = Sub ? (A-B) : (A+B); reg [1:0] Out; always @ (Sub or A or B) begin if (Sub) Out = A - B; else Out = A + B; end EECS150 Lab Lecture #2

21. Verilog <-> Hardware (4) reg [1:0] Out; always @ (posedge Clock) begin if (Reset) Out <= 2’b00; else Out <= In; end EECS150 Lab Lecture #2

22. Administrative Info • Cardkeys • Go to 253 Cory • Will be activated on: September 15th EECS150 Lab Lecture #2

23. Lab #2 (1) • Lab2Top • Accumulator • Stores sum of all inputs • Written in behavioral verilog • Same function as Lab1Circuit • Peak Detector • Stores largest of all inputs • Written in structural verilog EECS150 Lab Lecture #2

24. Lab #2 (2) EECS150 Lab Lecture #2

25. Lab #2 (3) Accumulator.v EECS150 Lab Lecture #2

26. Lab #2 (4) PeakDetector.v EECS150 Lab Lecture #2

27. Primitives (1) wire SIntermediate, SFinal, CPropagrate, CGenerate; xor xor1( SIntermediate, In, Out); and and1( CGenerate, In, Out); xor xor2( SFinal, SIntermediate, CIn); and and2( CPropagate, In, CIn); or or1( COut, CGenerate, CPropagate); FDCE FF( .Q( Out), .C( Clock), .CE( Enable), .CLR( Reset), .D( SFinal)); EECS150 Lab Lecture #2

28. Primitives (2) wire SIntermediate, SFinal, CPropagrate, CGenerate; xor xor1( SIntermediate, In, Out); and and1( CGenerate, In, Out); xor xor2( SFinal, SIntermediate, CIn); and and2( CPropagate, In, CIn); or or1( COut, CGenerate, CPropagate); FDCE FF( .Q( Out), .C( Clock), .CE( Enable), .CLR( Reset), .D( SFinal)); EECS150 Lab Lecture #2

29. Primitives (3) wire SIntermediate, SFinal, CPropagrate, CGenerate; xor xor1( SIntermediate, In, Out); and and1( CGenerate, In, Out); xor xor2( SFinal, SIntermediate, CIn); and and2( CPropagate, In, CIn); or or1( COut, CGenerate, CPropagate); FDCE FF( .Q( Out), .C( Clock), .CE( Enable), .CLR( Reset), .D( SFinal)); EECS150 Lab Lecture #2