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EE204 Computer Architecture

EE204 Computer Architecture. Processor Datapath. Homework 2 is out. Add. Read address. PC. Instruction. Instruction Memory. Instruction Datapath. 4. Instructions will be held in the instruction memory The instruction to fetch is at the location specified by the PC Instr. = M[PC].

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EE204 Computer Architecture

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  1. EE204Computer Architecture Processor Datapath Homework 2 is out. Hina Anwar Khan 2011

  2. Add Read address PC Instruction InstructionMemory Instruction Datapath 4 • Instructions will be held in the instruction memory • The instruction to fetch is at the location specified by the PC • Instr. = M[PC] • After we fetch one instruction, the PC must be incremented to the next instruction • All instructions are 4 bytes • PC = PC + 4 Note: Regular instruction width (32 for MIPS) makes this easy Hina Anwar Khan Spring 2011

  3. Instruction Registers R-type Instruction Datapath Read reg. num A Read reg num A Read reg data A Read reg num B Zero Result Write reg num ALU Read reg data B Write reg data • R-type Instructions have three registers • Two read (Rs, Rt) to provide data to the ALU • One write (Rd) to receive data from the ALU • We’ll need to specify the operation to the ALU (later...) • We might be interested if the result of the ALU is zero (later...) Hina Anwar Khan Spring 2011

  4. Data Memory Instruction Zero Registers Result Read reg. num A Read reg num A Read reg data A Read reg num B 16 32 signextend Write reg num Read reg data B Write reg data Memory Operations Read address Read data Write address Write data • Memory operations first need to compute the effective address • LW $t1, 450($s3) # E.A. = 450 + $s3 • Add together one register and 16 bits of immediate data • Immediate data needs to be converted from 16-bit to 32-bit • Memory then performs load or store using destination register Hina Anwar Khan Spring 2011

  5. PC + 4 Result Add Sh.Left2 Registers Read reg. num A Read reg num A Read reg data A Read reg num B Zero Result Write reg num Read reg data B Write reg data 16 32 signextend Branches • Branches conditionally change the next instruction • BEQ $2, $1, 42 • The offset is specified as the number of words to be added to the next instruction (PC+4) Instruction To controllogic • Take offset, multiply by 4 • Shift left two • Add this to PC+4 (from PC logic) offset • Control logic has to decide if the branch is taken • Uses ‘zero’ output of ALU Hina Anwar Khan Spring 2011

  6. Read reg. num A Read reg num A Read address Read reg data A Data Memory Read reg num B Instruction Registers Zero Read data 1 0 Write address Result Write reg num Read reg data B 1 0 Write data Write reg data 16 32 signextend Integrating the R-types and Memory MemoryDatapath • R-types and Load/Stores are similar in many respects • Differences: • 2nd ALU source: R-types use register, I-types use Immediate • Write Data: R-types use ALU result, I-types use memory • Mux the conflicting datapaths together • Punt on the control logic for now Hina Anwar Khan Spring 2011

  7. 4 Result Registers Add Read reg. num A Read reg num A Read address Read reg data A Data Memory Read reg num B Read address PC Zero Read data 1 Instruction [31-0] Write address Result Write reg num InstructionMemory 0 Read reg data B 0 Write data Write reg data 1 16 32 signextend Adding the instruction memory Simply add the instruction memoryand PC to the beginning of the datapath. Separate Instruction and Data memories are needed in order to allowthe entire datapath to complete its job in a single clock cycle. Hina Anwar Khan Spring 2011

  8. Registers 0 4 Read reg. num A Read reg num A Result 1 Read address Read reg data A Result Data Memory Add Read reg num B Sh.Left2 Add Zero Read data 1 Write address Result Write reg num 0 Read reg data B 0 Write data Write reg data 1 Read address PC Instruction [31-0] InstructionMemory 16 32 signextend Adding the Branch Datapath Now we have the datapath for R-type, I-type, and branch instructions. On to the control logic! Hina Anwar Khan Spring 2011

  9. When does everything happen? 0 4 Result 1 clk Add Result Sh.Left2 Add Single-Cycle Design Read reg. num A Read reg num A Read address Read reg data A Data Memory Read reg num B Read address PC Zero Read data 1 Registers Instruction [31-0] Write address Result Write reg num InstructionMemory 0 0 Read reg data B Write data Write reg data 1 clk clk 16 32 signextend Combinational Logic:Just does it! Outputs are always just a function of its inputs (with some delay) Registers: Written at the end of the clock cycle. (Rising edge triggered). Hina Anwar Khan Spring 2011

  10. Registers Read reg. num A Read reg num A Read reg data A Read reg num B Write reg num Read reg data B Write reg data What do we need to control? Mux - are webranching or not? Registers- Should we write data? 0 4 Result 1 Mux - Result fromALU or Memory? Add Result Sh.Left2 Add Read address Data Memory Read address PC Zero Read data 1 Instruction [31-0] Write address Result InstructionMemory 0 0 Write data 1 16 32 signextend Mux - Wheredoes 2nd ALUoperand come from? Memory-Read/Write/neither? ALU -What is theOperation? Almost all of the information we need is in the instruction! Hina Anwar Khan Spring 2011

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