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Interim Project Presentation

Interim Project Presentation . “Title of the Project”. Academic Guide:. External Guide:. Aim of the Project. To design PCI-E protocol and Verify the same with System Verilog VMM methodology. Project Objectives. To review literature on PCI-Express and existing PCI/PCI-X protocols

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Interim Project Presentation

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  1. Interim Project Presentation “Title of the Project” Academic Guide: External Guide:

  2. Aim of the Project To design PCI-E protocol and Verify the same with System Verilog VMM methodology.

  3. Project Objectives • To review literature on PCI-Express and existing PCI/PCI-X protocols • To review literature on VMM methodology and existing OVM and AVM methodologies • To obtain the design specifications and suitable architecture for PCI-E Protocol • To develop a Finite State Machine (FSM) for PCI-E and model the developed FSM in System Verilog • To create effective VMM based Verification environment and verify PCI-E with the developed Verification environment

  4. Methods and Methodology • Literature review on PCI-E and VMM Methodologies will be carried out by referring white papers, books, websites and related documents • Design specifications for PCI-E will be arrived at based on reviewed literature • Suitable architecture for PCI-E will be identified based on reviewed literature • Finite State Machine will be developed for PCI-E based on design functionality • Developed FSMs will be modeled individually in System Verilog to meet the specifications

  5. Methods and Methodology (cont..) • SystemVerilog Assertions will be implemented in the modeled RTL appropriately • Advantages and disadvantages of adding assertions to the design at the verification stage will be identified • VMM based verification environment will be developed and the various components required for verification will be identified • Methods will be adopted to increase the re-usability of Verification components • Methodology developed will be implemented and the overall system will be verified with Constrained as well as Random test vectors • Functional and Code coverage will be analyzed and methods will be adopted to improve the coverage

  6. Introduction

  7. Block Diagram

  8. Need for this work

  9. Design Details

  10. Progress work

  11. Progress work

  12. Place of work M. S. Engineering College Bangalore

  13. Project Schedule Project Schedule

  14. Resources • Software Resources • Synopsys VCS • Literature • Conference Papers • Books • Websites

  15. Literature • Conference Papers • Salem Emara, Lawrence Sasaki and Wayn Wu, A Formal Approach for PCI Express Validation with IFV, CDN Live 2005 • Renewei Wang and Zongyavo Wen, A Verification Environment for PCI-X BFM’s inVera, SNUG San Jose 2002 • Fadi Saibi and Jing-Fan Zang, Integrating a PCI Express Digital IP Core into a Gigabit Ethrnet Controller, SNUG 2006

  16. Literature (contd.) • 4. Rajeev Kumar, Advanced Switching based on PCI-E Architecture, ASI SIG Bus and Board Conference, January 2004 • T. Rktimaki and J.Numi, Reconfigurable IP Blocks : a Survey, System-on-Chip, 2004. Proceedings. 2004 International Symposium, pp. 117-122, November 2004 • 6. Clifford E. Cummings , SystemVerilog - Is This The Merging of Verilog & VHDL?, SNUG Boston 2003 16

  17. Literature (contd.) • Books • Ravi Budruk, Don Anderson and Tom Shanley, PCI Express System Architecture, Addison-Weley Pearson Edition, 2007 • Stuart Sutherland, Simon Davidman and Peter Flake, System Verilog for Design, 2nd edition, Springer, 2003 • Chris Spear, System Verilog for Verification, 2nd edition, Springer, 2004 • Janick Bergeron, Writing Test benches Using SystemVerilog, 2nd edition, Springer, 2006 • Janick Bergeron, VMM for System Verilog, 2nd edition, Springer, 2005 • Andrew Piziali, Functional Verification Coverage Measurement and Analysis, Kluwer Academic Publications, 2004

  18. Literature (contd.) • Websites • PCI Express Protocol Primer, http://www.compactpci-systems.com/articles/id/?3931/, as accessed in Sept 2009 • PCI Express Bus Description, http://www.interfacebus.com/Design_Connector_PCI_Express.html, as accessed in Sept 2009 • Assertionsin SystemVerilog:A Unified Language for More Efficient Verification, Tom Fitzpatrick, Synopsys Inc. http://www.synopsys.com/products/simulation/assert_sverilog_wp.pdf, as accessed in Aug 2008

  19. Benefits of the work • Will it result into a publication? Yes • Will it result into a product? No • Will it be a solution to an existing problem of an industry? Yes • Is it pursued for academic interest? Yes

  20. Thank You

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