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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

ELEC 5970-001/6970-001(Fall 2005) Special Topics in Electrical Engineering Low-Power Design of Electronic Circuits Pseudo-nMOS, Dynamic CMOS and Domino CMOS Logic. Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University

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Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering

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  1. ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic CircuitsPseudo-nMOS, Dynamic CMOSand Domino CMOS Logic Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC 5970-001/6970-001 Lecture 15

  2. Why Not Static CMOS? • Advantages: Static (robust) operation, low power, scalable with technology. • Disadvantages: • Large size: An N input gate requires 2N transistors. • Large capacitance: Each fanout must drive two devices. • Alternatives: Pass-transistor logic (PTL), pseudo-nMOS, dynamic CMOS, domino CMOS. ELEC 5970-001/6970-001 Lecture 15

  3. A Pseudo-nMOS Gate VDD VDD PUN Output Output PDN PDN Inputs Inputs CMOS Gate Pseudo-nMOS Gate ELEC 5970-001/6970-001 Lecture 15

  4. A Pseudo-nMOS Inverter 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Nominal device: W 0.5μ ── = ──── = 2 Ln 0.25μ W/Lp = 4 Output voltage, V W/Lp = 0.5 W/Lp = 1 W/Lp = 2 W/Lp = 0.25 0.0 0.5 1.0 1.5 2.0 2.5 Input voltage, V ELEC 5970-001/6970-001 Lecture 15

  5. Performance of Pseudo-nMOS J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003. ELEC 5970-001/6970-001 Lecture 15

  6. Negative Aspects of Pseudo-nMOS • Output 0 state is ratioed logic. • Faster gates mean higher static power. • Low static power means slow gates. ELEC 5970-001/6970-001 Lecture 15

  7. A Dynamic CMOS Gate VDD Output PDN CL Inputs CK ELEC 5970-001/6970-001 Lecture 15

  8. Two-Phase Operation in a Vector Period ELEC 5970-001/6970-001 Lecture 15

  9. 4-Input NAND Dynamic CMOS Gate VDD CK A B C D CK Output = CK’ + (ABCD)’∙ CK CL tL→H ≈ 0 ELEC 5970-001/6970-001 Lecture 15

  10. Characteristics of Dynamic CMOS • Nonratioed logic – sizing of pMOS transistor is not important for output levels. • Larger precharge transistor reduces output fall time, but increases precharge power. Faster switching due to smaller capacitance. • Static power – negligible. • Short-circuit power – none. • Dynamic power • no glitches – following precharge, signals can either make transitions only in one direction, 1→0, or no transition, 1→1. • only logic transitions – all nodes at logic 0 are charged to VDD during precharge phase. ELEC 5970-001/6970-001 Lecture 15

  11. Logic Activity • Probability of 0 → 1 transition: • Static CMOS, p0 p1 = p0(1 – p0) • Dynamic CMOS, p0 • Example: 2-input NOR gate • Static CMOS, Pdyn = 0.1875 CLVDD2fCK • Dynamic CMOS, Pdyn = 0.75 CLVDD2fCK p1=0.5 p1=0.25 p0=0.75 p1=0.5 ELEC 5970-001/6970-001 Lecture 15

  12. Charge Leakage CK Precharge Evaluate VDD Output A’ CK A=0 CK A’ CL Ideal Actual Time J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003. ELEC 5970-001/6970-001 Lecture 15

  13. Bleeder Transistor VDD VDD CK A B C D CK CK A B C D CK Output Output CL CL ELEC 5970-001/6970-001 Lecture 15

  14. A Problems With Dynamic CMOS VDD VDD CK A B C prech. evaluate CK A=0→1 CK CK CK B C J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003. ELEC 5970-001/6970-001 Lecture 15

  15. Domino CMOS VDD VDD CK A B C prech. evaluate CK A=0→1 CK CK CK C B R. H. Krambeck, C. M. Lee and H.-F. S. Law, “High-Speed Compact Circuits with CMOS,” IEEE J. Solid-State Circuits, vol. SC-17, no. 3, pp. 614-619, June 1982. ELEC 5970-001/6970-001 Lecture 15

  16. Bleeder in Domino CMOS VDD CK A B C D CK Output CL ELEC 5970-001/6970-001 Lecture 15

  17. Logic Mapping for Noninverting Gates AND A B C D E F G H ABC X Y G+H AND/OR ABC D E F G+H OR Y ELEC 5970-001/6970-001 Lecture 15

  18. Selecting a Logic Style • Static CMOS: most reliable and predictable, reasonable in power and speed, voltage scaling and device sizing are well understood. • Pass-transistor logic: beneficial for multiplexer and XOR dominated circuits like adders, etc. • For large fanin gates, static CMOS is inefficient; a choice can be made between pseudo-nMOS, dynamic CMOS and domino CMOS. ELEC 5970-001/6970-001 Lecture 15

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