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1. Power modeling flow for a power analysis at system levelCyril Chevalier, Audrey Le-Clercq, Diana MoisucSTMicroelectronicsPhilippe GarraultDocea Power

2. Content • Power modelingat system level: need, usage and requirement • IP power characterization • IP power modeling: HW power model, Use case power model • Hierarchical power modeling • Use case power modeling • Some system levelresults

3. ESL power analysis general purposes Trace from SW simulation or board validation Architectural performance model Use cases modeling Power model TLM/SystC virtual platform Thermal model SW Power aware SW simulation Aceplorer What for ? • POWER ARCHITECTURE EXPLORATION • POWER BUDGET TRACKING • THERMAL ANALYSIS • POWER MANAGEMENT SW HELP TO DECISION

4. Panic chez l’architect Sure, ourdevices are verycompetitivewith regards to power! Marketing to Customer: Marketing to System Architects: I need to model the power behaviour of the wholeSoC/chipset. I need to model all the use cases!! How do I get the data? Can I trust the data I amgetting? Can I trust my model?

5. System design flow TLM SystC platform availability Specification Validation RTL PG Early architecture Architecture validation Power aware SW development PM SW debug Performances architecture model SystC-TLM platform UC Power Tracking PM SW debug Power architecture model Dynamic thermal management simulation Thermal model

6. System modeling for accuracy : a bottom-up flow Use case analysis System architecture Use case description Swconstraints Performance analysis Power estimation AMS architecture RF architecture Soc architecture Power model for estimation Power model Power model Power model Power model Power model Power model 3rd party IP Sub-system 1 Sub-system 2 Sub-system 3 IP estimation IP estimation IP estimation IP estimation IP power estimation IP power estimation IP power estimation IP power estimation

7. IP Power characterization for power modeling • Power(Power Statei) = f(Param1, Param2,....) • Parameters: voltage, clock frequency, activity, process and temperature • IP Characterization process: • Power states & parameters identification • Characterization: Simulations, Measures • Conditions & Power figures reporting in a Power Card • Power model library Designer Architect Designer

8. Example: Audio Sub-System 5 power states Parameters 2 Power supplies: Vlogic, Vmem 3 clocks • 5 power states: • Idle, • Always On, • Music Playback, • CS Call, • Max Activity P(CS Call) = f(Vlogic, Vmem, Clock1, Clock2, Clock3)

9. IP power characterization flow Power figures collection : IP Power card IP level: Simulation environment Flow inputs levels Specification targets, IP description IP design flow Dynamic power card Activity file per power state : PSi RTL PwrEstimate Power states Dynamic pwr Per pwr state Gate Pwr Estimate Leakage power card Validation environment Pwr Measures Leakage per power state

10. IP Power Model generation IP Power card IP Power Model Aceplorer Power model generation Parameters default values Parameters default values Parameterized current equations Power model update Parameters • Equations of Dynamic and Leakage Power consumption IP power model library Each IP must have its Power Card IP Power Model IP Power Model IP Power Model IP Power Modeli

11. IP power use case model Scenario PS1 PS4 PS2 PS1 t2 t1 t4 t3 Pwr (W) IP power model Pwr(PS4) Pwr(PS1) Pwr( PS2) Pwr(PS2) Pwr(PS3) IP power states Pwr(PS1) Pwr(PS1) Pwr(PS4) IP UC Power Modeli Pwr(PS5) t2 t1 t4 t3 Pwr(PS6) IP Power Modeli IP Power Modeli Pwr(PS7) IP Power Modeli IP power model library

12. Hierarchical model & scenario creation time Vdd2 Vdd1 • IP power model library • Power model • UC model Top MC1-PS1 TL-PS1 TL-PS4 C3-PS4 TL-PS2 C3-PS2 MC1-PS2 TL-PS1 C3-PS1 MC1 C2 MC1 MC3 MC2 C3 C2 C1 instantiation Modeling Interface Hierarchy capture Hierarchical power model and scenario generation Aceplorer Scenario description Aceplorer

13. Conclusion Power modeling flow • Formal modeling flow : model standardization • Data traceability • Easier model debug • High readability : communication tool bw many users • Fast system power model development • Upgradeable models for accuracy as needed Next work • use cases power trace usage • Use cases development for power model correlation with on board validation