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Paper Report

Paper Report. Systematic Software-Based Self-Test for Pipelined Processors. Mihalis Psarakis Dimitris Gizopoulos Miltiadis Hatzimihail Dept . of Informatics , University of Piraeus, Greece Antonis Paschalis Dept. of Informatics & Telecomm ., University of Athens, Greece

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Paper Report

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  1. Paper Report Systematic Software-Based Self-Test for Pipelined Processors MihalisPsarakisDimitrisGizopoulosMiltiadisHatzimihail Dept. of Informatics, University of Piraeus, Greece AntonisPaschalis Dept. of Informatics & Telecomm., University of Athens, Greece AnandRaghunathanSrivathsRavi NEC Laboratories America, Princeton, NJ, USA DAC2006, July24-28,2006, San Francisco, California, USA. Presenter: Jyun-Yan Li

  2. Abstract • Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in Systems-on-Chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST eliminates the need for high-cost testers, and enables high-quality at-speed testing. Thus far, SBST approaches have focused almost exclusively on the functional (directly programmer visible) components of the processor. • In this paper, we analyze the challenges involved in testing an important component of modem processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are insufficient to test the pipeline logic, resulting in a significant loss of fault coverage. We further identify the testability hotspots in the pipeline logic. Finally, we develop a systematic SBST methodology that enhances existing SBST programs to comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology), and can reuse the test development effort behind existing SBST programs.

  3. Abstract (cont.) • We applied the methodology to two complex, fully pipelined processors. Results show that our methodology provides fault coverage improvements of up to 15%(12% on average) for the entire processor, and fault coverage improvements of 22% for the pipeline logic, compared to a conventional SBST approach.

  4. Related work Component-oriented SBST [8] Generate test pattern for functional behavior [2,3,4] Advance SBST [9,10] testability [12] Random or pseudorandom instruction sequence Testing for complex RISC Systematic testability analysis of pipelined logic Function components self-test routines for ISA and RTL No provide fault coverage for entire processor No hazard dection & data forwarding miniMIPS & OpenRISC 1200 [14,15] This paper

  5. What is the Problem • Testability • Logic carrying address-related information • Pipelined register of address information is used by other components • ex: bus controller, program counter, exception unit • Hazard detection and forwarding • input data is from forwarding unit rather than from source register

  6. Address-related • Partition SBST program into multiple code segment and divide virtual memory into some regions • Load code segment into region in virtual memory • Mapping virtual memory to instruction memory 0, m/r-1, 2m/r-1

  7. Address-related observability Path1 : PC and IF fault propagated to address bus through bus controller Path2 : ID and EX fault Path3 : use link instruction occur in the ID and EX Path4 : use exception occur in the EX and MEM

  8. Hazard detection and forwarding • Processor has n stages • Ia: result at p stage, store at s stage • Ib: read at d stage, actually need at f stage • Lemma 1 • If s-d < c , no hazard , c:distance between two instruction • If s-d ≥ c , hazard • If p-f ≥ c , unresolved • If p-f < c , can resolved

  9. Proposal Method Functional SBST code Phase 1 All possible dependencies between instructions Data dependency & loop Identification of def-use pairs forwarding Pipeline description Generation of test code variants loop unrolling 1. N stage 2. Each stage function 3. Forwarding path Modification of the SBST code Enhanced code Phase 2 Memory and cache parameters Partition of SBST program Address-related 1. Virtual memory size 2. Physical memory size 3. Program size Insertion of jump instructions Address faults propagation Enhanced SBST code

  10. Experimental results • miniMIPS: 100MHz and 32817 gates • OpenRSIC: 102MHz and 35657 gates • Improve 22% for pipeline

  11. Experimental results (cont.) • Fault coverage improve 12% on an average for entire processor Original With multiplier Without multiplier

  12. Conclusion • This paper present an enhance SBST methodology for pipelined processor • Address-related component • Hazard detection and forwarding mechanism

  13. My comment • Using lemma 1 to verify forwarding unit for different processor • It not describe how to loop unrolling and select code variants clearly

  14. Generating and combining code variants

  15. Selection of code variants

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