Paper Report

1. Paper Report Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors AntonisPaschalis Department of Informatics & Telecommunications University of Athens, Greece DimitrisGizopoulos Department of Informatics University of Piraeus, Greece Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’04) Citing count: 12 Presenter: Jyun-Yan Li

2. Abstract • Software-based self-test (SBST) strategies are particularly useful for periodic testing of deeply embedded processors in low cost embedded systems that do not require immediate detection of errors and cannot afford the well-known hardware, software, or time redundancy mechanisms. • In this paper, first, we identify the stringent characteristics of an SBST test program to be suitable for on-line periodic testing. Then, we introduce a new SBST methodology with a new classification scheme for processor components.

3. Abstract (cont.) • After that, we analyze the self-test routine code styles for the three more effective test pattern generation (TPG) strategies in order to select the most effective self-test routine for on-line periodic testing of a component under test. • Finally, we demonstrate the effectiveness of the proposed SBST methodology for on-line periodic testing by presenting experimental results for a RISC pipeline processor.

4. What is the Problem • On-line test divides into concurrent and non-concurrent • Concurrent utilizes hardware redundancy techniques • Large increase silicon area • Non-concurrent is useful for periodic testing • Usually use hardware-based self-test (HBST) for on-line periodic testing • Decrease performance, hardware overhead and increase power consumption for embedded processor • Using software-based self-test (SBST) • Generates high fault coverage test program • Small memory footprint, small execution time and low power consumption

5. Related work SBST high abstraction level as Instruction Set Architecture targeting processor Components as RTL descriptions MIPS Plasma [13] functional structural 3 stage pipeline with forwarding RISC processor Targeting processor components [8-10] randomized [5-7] Divide and conquer High fault coverage, but large number of instruction Regular deterministic TPG [9-10] Test the critical components, like arithmetic & logic, register files Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors This paper:

6. On-line periodic test program characteristics • Test program execution time < a quantum time cycle • If > quantum time, context switch overheads • Without unresolved data hazards • Reduce pipeline stall cycles • Temporal locality for loop, spatial locality for sequentially executed instruction • Reduce memory stall cycles • Small data structured in arrays • Reduce memory stall cycles

7. SBST Methodology • Information extraction • Identify the component’s inputs and outputs • Multiplexers Near input and out • Identify instruction that carry out specific operation • Identify appropriate instruction(s) to control them Phase A Information Extraction Component Classification & Test Priority (visible, partially, hidden) Phase B Self-Test Routine Development (selection among 3 TPG strategies) Phase C

8. Component classification • Visible components (VC) • Data VC (D-VC) • ALU, shifter, register file, data field of pipeline register • Address VC (A-VC) • Instruction fetch unit, memory address register • Mixed (address-data) VC (M-VC) • PC-relative addressing • Partially visible components (PVC) • Generate control signal as Processor Control Unit • implemented as FSM • Hidden components (HC) • Increase performance • Forwarding unit, hazard detection unit

9. Test priority Data visible components (D-VC) Input: (1) immediate (2) register (3) data memory Output: (1) register file (2) data memory (3) data register Partially visible components (PVC) Test priority Affect the operation of visible components Address visible components (A-VC) A lot of memory reference & cache miss overhead Mixed visible components (M-VC) A lot of memory reference & cache miss overhead

10. Deterministic ATPG based TPG strategy • Combinational D-VC, Low gate-level • 2 ways: • Immediate addressing • In the memory and loop-based routine fetch Immediate addressing Loop-based Under test instruction Store final result to memory

11. Psedorandom based TPG strategy • Combinational D-VC, low gate-level • Loop-based software LFSR self-test routine Implement software LFSR Under test instruction Store final result to memory

12. Regular deterministic based TPG strategy • Combinational or sequential D-VC, High-level • 2 ways: • Immediate addressing • In the memory and loop-based routine fetch Under test instruction Store final result to memory

13. Comparing 3 strategy (*): no describing in the paper

14. Experimental result • 32 bits, 3 stage pipeline with forwarding MIPS processor • 26080 gates by 0.35um • Cache miss rate = 5%, miss penalty = 20 clock cycle • quantum time cycle = 11000 80 for testing memory controller 7 for unloaded to data memory

15. Conclusion • 3 SBST strategy for on-line periodic testing • Deterministic ATPG based • Psedorandom based • Regular deterministic based • To improve reliability of embedded system • My comment • Aim processor component • The programmer have to know the most critical component • How to compact test responses