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Resets & Interrupts

Resets & Interrupts. • Power-On Reset. • External Hardware Reset. • Crystal Monitor. • Computer Operating Properly Real time interrupt. • Initiated by positive transition on VDD. 8192 E clock delay is built in to allow oscillator to stabilize. Power On Reset. 8192 ECLK

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Resets & Interrupts

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  1. Resets & Interrupts

  2. • Power-On Reset • External Hardware Reset • Crystal Monitor • • Computer Operating Properly • Real time interrupt

  3. • Initiated by positive transition on VDD. • 8192 E clock delay is built in to allow oscillator to stabilize. Power On Reset 8192 ECLK Cycles 64 ECLK Cycles 128 ECLK Cycles VDD CPU CLK DATA BUS/ ADDRESS BUS IRESET V F P P P FFFE FFFE 1st Opcode 2nd Opcode 3rd Opcode V - VECTOR FETCH F - FREE CYCLE P - PROGRAM FETCH Internal Reset is held low by MCU For about 8192 E clocks • In General: Subsystems and control bits are initialized to have least effect on system ( I.e. interrupts masked, ports read only, serial communication disabled,...)

  4. External & InternalResets 96 E Clocks 64 ECLK CYCLES 32 ECLK CYCLES CPU CLK DATA BUS/ ADDRESS BUS RESET IRESET 3nd Opcode FFFE FFFE 1st Opcode 2nd Opcode SAMPLE PIN • RESET pin asserted for > 2 E clocks. • RESET pin must negate before reset service can begin. • No delay to stabilize oscillator.

  5. Crystal Monitor (1 of 2) Useful for: 1. Automatic Reset from a slow or stopped clock. 2. Improves fault tolerance of system. Description: If the E clock drops below a frequency of 10 KHZ* and the Crystal Monitor function has been enabled, then: 1. system reset is asserted on the external reset pin. 2. Crystal Monitor vector is fetched. Else Enter Self Clock Mode if Enabled * IF E CLOCK FREQUENCY > 10KHz and < 500KHz, THEN A CLOCK MONITOR RESET MAY OCCUR. ( NOT GUARANTEED ) Note: Crystal Monitor Time-out range 2usec - 150 usec.

  6. Crystal Monitor (2 of 2) PLLCTL - CRG PLL Control Register Address Offset $0006 CME - Crystal Monitor Enable 1 = Monitor is enabled 0 = Monitor is disabled Crystal Monitor function can be enabled/ disabled at any time. When the Crystal Monitor is enabled, a slow or stopped clocks, (including the Stop instruction) causes a crystal failure to: 1. Reset the MCU (Fetch CM Vector from $FFFC-$FFFD) or 2. Enter self-clock mode PINS: 1. RESET – Asserted for 64 E clocks.

  7. Crystal Loss/Stop & Reset Recovery Sequence Stop Instruction Clock Failed Power-On CME = 1 & SCME =0 ? CME = 1 & SCME =0 ? Yes Yes MCU Resets MCU Resets No No Stop Mode Interrupt ? Clock ? No No Count 8192 OSCLK Note2:Self Clock Mode Frequency Range = 2.5MHZ - 5.5MHZ Yes Yes SCME =1 ? Clock ? Yes No Assert SCM & SCMIF No Yes Clock ? MCU Enters Self CM No Wait for Clock Yes Count 8192 OSCLK Note1:Crystal Monitor Timeout Range 6 - 18.5 us Count 8192 OSCLK Yes Clock ? No Clocks Released Negate SCM Clocks resume Normal Operation Resume Normal Operation

  8. Computer Operating Properly (1 of 3) Useful for: 1. Insuring that the MCU does not get "hung up" for an extended period of time. 2. Improves fault tolerance of system. Description: If the COP rate select bits are not “0” and if the watchdog timer is not reset within a specified time period: 1. Then a system reset is asserted on the external reset pin. 2. COP vector is fetched ( $FFFA-$FFFB ) Pins: 1. Reset - Asserted for 64E clocks.

  9. Computer Operating Properly (2 of 3) COPCTL - CRG COP Control Register Address Offset $0008 WCOP - Window COP Mode 1 = Window COP operation (Writes to ARMCOP Register must occur in the last 25% of selected period). 0 = Normal COP operation CR[2:0] - COP Watchdog Timer Rate Select COPCTL : Write Once in user mode, anytime in test mode. A write to COPCTL will initialize COP counter . ARMCOP - CRG COP Arm/Reset Timer Address Offset $000E – Software writes $55 followed by $AA to ARMCOP, to reset internal COP counter. PINS 1. RESET Asserted for 64 E clocks

  10. COP Time-out Period Select (3 OF 3) CR[2:0] = 000 - COP is Off OSCCLK COP Rate Selection Bit Definition COP Divider Chain Time-Out = WindowEnd = OscClkPeriod * (OscClkDivider +3) Window-Start = OscClkPeriod * ((0.75* OscClkDivider) + 9)

  11. Determining Reset Source N CLOCK START CME=1 ? END FAILS GO TO COP ROUTINE GO TO GO TO CRYSTAL MONITOR ROUTINE Y RESET SERVICE ROUTINE ASSERT CLOCK RESET PIN MONITOR FOR 64 STATUS IS EXTERNALLY E-CLOCK LATCHED ASSERTED CYCLES RESET Y Y RESET PIN RESET PIN STILL LOW ? CRYSTAL MONITOR SYSTEM RESET ? N NEGATION, N 32 E-CLOCK CYCLES ALLOWED RESET PIN STILL LOW?

  12. INTERRUPT EXCEPTIONS INTERRUPT STACK PRIORITIES VECTORS INTERRUPT FLOW INTERRUPT INSTRUCTIONS STANDBY MODES

  13. Interrupt Sources From COP From Crystal Monitor From P.I.T INTERNAL BUS EXTERNAL BUS C.M RESET COP RESET P.I.T IRQ ECT IRQ’S SPI IRQ’S SCI IRQ’S Other IRQ’S Resets SWI ILLOP I_Vector X_Vector IPEND XPEND IRQ XIRQ RESET INTERRUPT & RESET VECTOR GENERATION & PRIORITY The MC9S12DP256 can generate over 50 Interrupt requests

  14. Interrupt Stacking Order SP after operation SP-9 CCR SP-8 D SP-6 X SP-4 Y SP-2 PC xx SP before operation SP When HCS12 acknowledges an interrupt, it stacks registers, then determines which vector to take. ( different from hc11 ). Note: Stack operation is performed in 5-bus cycles even if SP is misaligned.

  15. * Can generate external Reset ** Once enabled, cannot be masked Non-Maskable Exception Priority • More than 40 interrupt sources. • Separate vector for each Reset / Interrupt source. • 6 Non-Maskable sources 1. RESET 2. Crystal Monitor* 3. COP WATCHDOG* 4. TRAP 5. XIRQ** 6. SWI

  16. Interrupt Vector Table (1 of 3)(64 Exception Vector Entries)

  17. Interrupt Vector Table (2 of 3)

  18. Interrupt Vector Table (3 of 3)

  19. Interrupt Request Pins Control HCS12 IRQ - Masked by I-Bit in CCR XIRQ - Masked by X-Bit in CCR* * Once enabled, can not be masked INTCR - Interrupt Control Register Address Offset $001E Write once IRQE - Interrupt Select Edge Sensitive 1 = IRQ PIN is configured for negative edge 0 = IRQ PIN is configured for level sensitive IRQEN - External IRQ Enable 1 = IRQ PIN is connected to interrupt logic 0 = IRQ PIN is disconnected from interrupt logic Note: XIRQ and IRQ have internal pull-ups and enabled out of reset Pull-up can be turned off by clearing PUPEE in PUCR register

  20. Interrupt & Priority Control An interrupt source can be elevated to highest priority( i.e. 7 ) by writing to HPRIO register ( bits 7 - 1 ). Interrupt priority can only be changed when I = 1 in CCR HPRIO - High Priority Register Address Offset $001F To promote an interrupt the user writes the least significant byte of the associated interrupt vector address to this register. If an unimplemented vector address or a non I-masked vector address (value higher than $F2) is written, then $FFF2 vector will be the default. (highest priority interrupt).

  21. Interrupt Flow SOFTWARE HARDWARE INTERRUPT INTERRUPT N Y STACK MPU MASK CONTINUE MAIN REGISTER SET? PROGRAM CONTENTS SET I BIT IN CCR $FF80 LOAD INTERRUPT VECTOR INTO VECTOR TABLE PROGRAM COUNTER $FFFF EXECUTE INTERRUPT SERVICE ROUTINE

  22. Interrupt Instructions FUNCTION MNEMONIC OPERATION SOFTWARE INTERRUPT SWI REGS M  SP SP-9 SP  1 I  M PC  FFF6 H M PC  L FFF7 RETURN FROM INTERRUPT RTI M REGS  SP  SP + 9 SP Note: RTI instruction will not unstack if another interrupt is pending.

  23. Real-Time Interrupt Useful for: 1. Keep track of time 2. Initiate tasks on periodic bases. Description: When a time-out occurs: 1. Interrupt request to CPU is generated, if enabled 2. RTI vector is fetched ( $FFF0-$FFF1 )

  24. Real-Time Interrupt Flow Chart COUNT IS AT AN INTERVAL ? Y INCREMENT INTERNAL COUNTER RTIF GOES to 1 START N N RTIE=1 ? END Y ASSERT INTERRUPT

  25. Real-Time Control/Status Registers RTICTL - Real-Time Clock Control Register Address Offset $0007 Bit 7 6 5 4 3 2 1 0 Reset: 0 0 0 0 0 0 0 0 OSCCLK RTR[6:4] - Real-Time Interrupt Prescale Rate Select RTR[3:0] - Real-Time Interrupt Modulus Counter Select RTI Divider Chain Note: To initialize the internal RTI counter, write to the RTICTL register.

  26. PLL Control Registers CRGFLG - CRG Flag Register Address Offset $0003 RTIF — Real Time Interrupt Flag RTIF bit is automatically set to one at the end of every RTI period. This flag can only be cleared by writing a 1. 0 = Time-out has not yet occurred. 1 = Set when the time-out period is met. CRGINT - CRG Interrupt Enable Register Address Offset $0004 RTIE - Real-Time Interrupt Enable 0 = Interrupt is disabled 1 = Interrupt is disabled

  27. S12 Oscillator Layout Oscillator components on MCU side of board - no vias No ground or power planes under Oscillator components, to minimise parasitics.* Optional dc blocking capacitor goes in the EXTAL line here RESET signal noise free. Don’t use for external signals and / or add series filtering. PLL Filter cct C2 C1 Y1 R2 C3 TEST XTAL EXTAL VSSPLL C4 XFC VDDPLL No other signals should be routed near, or under the crystal components or the PLL components because these circuit nodes are very susceptible to coupled electric noise. RESET To 5V ‘star’ point at VSSA C5 C6 C7 VDDR VSSR C8 C9 PE4 Good isolation of PLL / Oscillator Power supply. C5 = 1nf, C6 = 100nF. Low impedance, no vias. * NOTE: EMC considerations should also be taken into consideration Connection to ground net/plane

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