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Evolvable Hardware (EHW)

This topic review explores the concept of evolvable hardware (EHW), its applications, and the challenges faced in circuit design. The use of genetic algorithms and FPGAs for EHW is discussed, along with the evaluation methods used to assess fitness. The potential benefits and limitations of EHW are examined, providing insight into its potential future developments.

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Evolvable Hardware (EHW)

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  1. Evolvable Hardware(EHW) Topic Review S08*ENGG*6530 Antony Savich

  2. Topic Review Outline • Motivation • Concept details • Problems and bottlenecks • General applications • Personal Retrospect • Conclusion • Design project summary S08*ENGG*6530 - EHW

  3. References • Jim Torresen, An Evolvable Hardware Tutorial. In proc. of 14th International Conference on Field Programmable Logic and Applications (FPL'2004), August 2004, Antwerp - Belgium • P Haddow, G Tufte, P Van Remortel, Evolvable hardware: pumping life into dead silicon. In OnGrowth, Form and Computers.Sanjeev Kumar, Peter J. Bentley, Editors.Elsevier, 2003 • Langdon, W.B. and Gustafson, S. (2005) Genetic Programming and Evolvable Machines: five years of reviews. Genetic Programming and Evolvable Machines, 6 (2). pp. 221-228. Springer, 2005 S08*ENGG*6530 - EHW

  4. What is Evolvable Hardware? • EHW is hardware which is generated or regenerated by special means • Goal: improve circuit performance parameters via dynamic autonomous regeneration • speed, area, power, output quality • Hardware Auto Evolution S08*ENGG*6530 - EHW

  5. What do we normally do? • Hardware engineering • Application analysis • Requirement specification • Circuit design (RTL, layout, routing) • Test suite formulation • Circuit verification and validation • Simulation • Hardware • Field performance evaluation S08*ENGG*6530 - EHW

  6. What do we normally do? S08*ENGG*6530 - EHW

  7. Why should we bother? • From design specification on, • 85% (approx) of human time is spent on product (circuit) generation • Design complexity exponentially increases • Easy to hierarchaly specify • Difficult to optimize as a whole • Human time = expensive • Machine time = cheap……. S08*ENGG*6530 - EHW

  8. Why should we bother? • Sizing limitation is not valid (Moore’s law) • ~1billion transistors per chip (Intel 2006) • How much is this better than ~100million tr. chips? • Designability is the current hurdle • Nowadays, improvement in transistor count does not equate to a similar functional or performance improvement, the gap grows… S08*ENGG*6530 - EHW

  9. What is the benefit? • If it were possible to evolve inefficient circuits… • The circuits created by evolution can be: • much simpler than human creations • not always comprehendible by humans S08*ENGG*6530 - EHW

  10. By autoevolution we get… • Reduced complexity, smaller circuits • In turn helps simplify the evolutionary process • More efficient circuits • Better performing circuits • New ideas and innovation • At the expense of machine time… gives us extra time to do other things than do boring circuit design? S08*ENGG*6530 - EHW

  11. How do we do it? Specification S08*ENGG*6530 - EHW

  12. How do we do it? • Usually implies evolutionary techniques: • Genetic Algorithms • Genetic Programming • Evolutionary Programming S08*ENGG*6530 - EHW

  13. How do we do it? • Can be applied to various circuits • Digital (commercial or custom) • Analog • Off-line or on-line evolution S08*ENGG*6530 - EHW

  14. How do we do it? Use requirements Random using defined representation Determine fitness Implement on technology Evolve S08*ENGG*6530 - EHW

  15. How do we do it? Ideas? Need to map a circuit description (phenotype) to an evolutionary technique description (genotype) How do we represent a circuit? Random using defined representation S08*ENGG*6530 - EHW

  16. How FPGAs are relevant? • FPGAs are a natural example of reconfigurable digital technology • Can use the programming bitstream as the genotype directly • Can rapidly reconfigure to fit new solutions S08*ENGG*6530 - EHW

  17. How do we do it? Need to evaluate generated circuits (typically many) Assign a fitness parameter How would you normally evaluate a circuit? S08*ENGG*6530 - EHW

  18. Evaluation methods S08*ENGG*6530 - EHW

  19. How do we do it? What are the evaluation criteria for fitness? Use requirements S08*ENGG*6530 - EHW

  20. Problem Redefinition • Sometimes… • The task of finding a solution is redefined as a task of • Specifying the problem • Representing the solution • Sometimes, one is not easier than the other S08*ENGG*6530 - EHW

  21. How do we do it? This step depends on the algorithm you choose, In EHW this is typically GA (genetic algorithms) Evolve S08*ENGG*6530 - EHW

  22. Genetic Algorithm Initial circuit population using a chosen representation Parents Evolution Children S08*ENGG*6530 - EHW

  23. A cycle of evolution S08*ENGG*6530 - EHW

  24. Issues by design… • Using FPGAs leads naturally to direct mapping (genotype – phenotype) • Creates a search space explosion for larger circuits • Indirect mapping – reduces genotype description vs. phenotype requirements • Less information in genotype, not all phenotypes are mapped (best solution may be skipped) • Changes complexity of finding a best solution into complexity of finding the right mapping to include it S08*ENGG*6530 - EHW

  25. Issues by design… • Representation of genes – quick failure • If short, 1’s or 0’s, a single bit mutation may lead to complete circuit failure • It’s difficult to encode genes in a genotype such that a small gene change will result in small functionality change S08*ENGG*6530 - EHW

  26. Issues by design… • Technological evolution is a problem • Better flexibility means increased granularity • Increased complexity means larger phenotype • Larger phenotype means slower configuration times • New heterogeneous FPGA features pose mapping difficulties – not EHW friendly. • Complexity of system means complexity of fitness functions, longer evaluation times S08*ENGG*6530 - EHW

  27. Solutions • ‘Virtual’ FPGAs are possible: • Reduce genotype by simplifying routing choices; logic component choices • Can be mapped onto commercial FPGAs S08*ENGG*6530 - EHW

  28. Solutions • Development of EHW friendly features • Map only the features that are suitable for evolution • Partially evolvable systems • Design most of the system (fixed portion) • Allow only a portion to be evolved S08*ENGG*6530 - EHW

  29. An Interesting Application • On-line evolutionary systems: • Create competing nodes • Operate one in real time • Evolve others in parallel • Another reaches maturity - swap S08*ENGG*6530 - EHW

  30. Personal Retrospective: 1 • On-line HW/SW evolvable system: • Why only require hardware execution vs. software processing? • Why only evolve hardware? • The key – hardware/software cohabitation within an on-line self-evolvable system. S08*ENGG*6530 - EHW

  31. Personal Retrospective: 1 Evolving a scheduled Unit (co-evolution) Scheduled for optimization Load monitor & scheduler Task set {1..n} Task set {1..m} Hard model Soft model With current advances in self-reconfiguration technology and device size, this is all possible as a SoC! S08*ENGG*6530 - EHW

  32. Personal Retrospective: 2 • Current research: Neural Network (ANN) implementations • Rough model of the brain • ANNs provide approximating solutions to problems • ANNs are trained on a sample of the problem space • Quality of results highly depends on parameters used in constructing ANN: • Topology (number and type of neurons) • Arithmetic representation • Learning function S08*ENGG*6530 - EHW

  33. Personal Retrospective: 2 • Fitness determined by training a configuration • Training is expensive, best done in hardware (currently FPGA), many configs to train • This process can benefit from automated design evolution, the technology is directly correlated with EHW methods: S08*ENGG*6530 - EHW

  34. Summary: EHW Evolved using GA Reduce- Encoded by Represented by Need a Genotype 101011 Phenotype 1011010101010100 Circuit Fitness Technology Evaluated Implemented on S08*ENGG*6530 - EHW

  35. Topic Conclusion • Evolvable Hardware – great circuits made easy (in theory) • Typically Genetic Algorithm is used to evolve • Rephrases the “circuit design” problem into the “pheno-genotype... mapping” problem. • Currently, can evolve small circuits • New hardware not friendly S08*ENGG*6530 - EHW

  36. Course Project Direction • Take an existing architecture • monolithic, full hardware acceleration • a type of ANN for this project • Use Tensilica tools • Profile and map portions of hardware to produce: • software execution + smaller accelerator • Goal: compare resulting performance vs. consumption of FPGA resources. S08*ENGG*6530 - EHW

  37. Thank you S. Dali, Man with His Head Full of Clouds, 1936 S08*ENGG*6530 - EHW

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