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IP Protection. Graduate Inst. of EE. NTU Chia-Chao Rodion Kan 2008.1.28. OUTLINE. INTRODUCTION PRELIMINARIES SCHEME. INTRODUCTION PRELIMINARIES SCHEME. INTRODUCTION. Provide a key unique each chip to activate its functionality. FUNCTIONALITY ENABLE!. valid key. UNCORRECT
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IP Protection Graduate Inst. of EE. NTU Chia-Chao Rodion Kan 2008.1.28
OUTLINE • INTRODUCTION • PRELIMINARIES • SCHEME
INTRODUCTION • PRELIMINARIES • SCHEME
INTRODUCTION • Provide a key unique each chip to activate its functionality. FUNCTIONALITY ENABLE! valid key UNCORRECT FUNCTIONALITY! invalid key
INTRODUCTION • PRELIMINARIES • SCHEME
PRELIMINARIES • Initialization of sequential circuits • Explicit reset circuits • Implicit reset circuits • Explicit + implicit reset circuits • The Random Unit Block (RUB) • A circuit gives each chip an ID • Due to process variation
PRELIMINARIES • Minimum Feedback Vertex Set (MFVS) • Feedback vertex set • Given G = (V, E), a subset F of V such that every directed cycle in G contains at least one vertex in F. • Minimum feedback vertex set • A subset F of V such that the cardinality |F| is minimum among all possible feedback vertex sets.
PRELIMINARIES • Reset the circuit by explicit resetting the MFVS
INTRODUCTION • PRELIMINARIES • SCHEME
SCHEME • Feed the RUB outputs (ID) to some registers in the MFVS • Goal: given reset state s and the MFVS Find subset A of the MFVS, initial value i of the registers in MFVS\A such that whatever the initial value of A is, there is a reset sequence to s. • Feed the RUB outputs to A
SCHEME • P: states which can transit to s P = Pre_image*(s) • V: initial value of the MFVS which can reset to P • Ri is the registers that been reset after i clock cycles • A , i can be found by checking the V set
SCHEME • Example: V = {1000011, 1001101, 1011101, 1101101, 1111101, 0110110, 1000111, 0110001} A={r2,r3} ← feed with RUB i =11101 ← initail value to MFVS/A
That’s all! Thank You! Q & A
BACKGROUND • Resettability analysis • Initialization of sequential circuits • Pixley’s resettability analysis • Heuristics to alleviate the state explosion problem in resettability analysis • The Random Unit Block (RUB)
RESETTABILITY ANALYSIS • Term Definition • Initial state • Reset sequence • Reset state
RESETTABILITY ANALYSIS • Initialization of sequential circuits • Hardware reset circuit • Reset sequence • A combination of the above two: • Hardware reset + reset sequence • Explicit reset register • Implicit reset register
RESETTABILITY ANALYSIS • Pixley’s resettability analysis • Goal: Find a reset sequence for a given FSM • Based on Universal Alignment Theorem • Result from Universal Alignment Theorem Given an FSM M with S being the set of all states of M, let . Then there exists a reset sequence if and only if
Heuristics • State explosion problem • Heuristic without resettability analysis • Register Dependency Graph (RDG) Corresponding RDG A sequential circuit
Heuristic without resettability analysis • Goal: Find a minimal set of explicit reset registers → a maximal set of implicit reset registers → The Max Independent Set problem (NP-complete)
Heuristic without resettability analysis • Example with input length 1
Heuristic with resettability analysis • Goal Further reduce the number of explicit reset registers as well as to alleviate the state explosion problem
The Random Unit Block • RUB: Unique ID to each chip due to process variation • Example: The PUF circuit
SCHEME • Idea: • Calculate the initial explicit reset register set. (Heuristic) 2. Choose the subset of explicit reset registers and their reachable registers for being the state variables. (Heuristic) • Doing resettability analysis of the state variables to all possible conditions of the unchosen explicit reset registers. If each returns a reset sequence, record them. Otherwise, back to step 2, and eliminate another subset of explicit reset register. 4. Feed the RUB output to the resulted explicit reset register set.
SCHEME • ANALYSIS: • Pros: • By applying certain input sequence, each chip can be reset to a particular reset state after power on. • For different RUB output, the generated reset sequence might be different. (Still need a strict analysis) • Cons: • Different chips may have different reset states due to the different result from resettability analysis for their RUB output. • The computation complexity of Step 3 in the scheme is high. (Exp-time to the number of explicit register for all conditions and Exp-time to the number of state variables for resettability analysis)
REFERENCES [1] Carl Pixley, A Theory and Implementation of Sequential Hardware Equivalence, 1992. [2] Carl Pixley, Seh-Woong Jeong, and Gary D. Hachtel, Fellow, IEEE, Exact Calculation of Synchronizing Sequences Based on Binary Decision Diagrams, 1994. [3] Chung-Min Li, Effective FSM Initialization Using Structural and State Based Reset, 2007. [4] Jae W. Lee, Daihyun Lim, Blaise Gassend, G. Edward Suh, Marten van Dijk, and Srini Devadas, A Technique to Build a Secret Key in Integrated Circuits for Identification and Authentication Applications, 2004. [5] Y. Su, J. Holleman, B. Otis, A 1.6pJ/bit 96% Stable Chip-ID Generating Circuit using Process Variations, 2007. [6] Yousra Alkabani, Farinaz Koushanfar and Miodrag Potkonjak, Remote Activation of ICs for Piracy Prevention and Digital Right Management, 2007. [7] Yousra M. Alkabani, Farinaz Koushanfar, Active Hardware Metering for Intellectual Property Protection and Security.
Thank You! Q & A