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L1 Pixel Trigger Status Report

This report provides updates on the Pixel and Muon L1 Trigger Task Group's progress, including the implementation of the BB33 algorithm, coordination between Muon and Pixel WBS, and integration of L2 and L3 Trigger processors. It outlines objectives such as optimizing algorithm implementation and improving processing time estimates. The report also discusses the development of DSP Farm Prototypes, data flow analysis, and future tasks for the BTeV Technical Design.

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L1 Pixel Trigger Status Report

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  1. L1 Pixel Trigger Status Report

  2. BTeV L1 Trigger Task Group • Erik Gottschalk • Vince Pavlicek • Ken Treptow • Ted Zmuda • Greg Deuerling • David Berg • Mike Haney (-trigger) • Mike Wang • Xiaonan Li • Gustavo Cancelo • Jinyuan Wu (?)

  3. WBS • L1 Trigger Task WBS (Vince,Mike H, Gustavo, Erik) • WBS work started about 3 months ago • Current version of Pixel L1 and Muon L1 WBS is V9 • 2nd revision after management feedback suggestions. • Muon and Pixel WBS coordination • L2 and L3 Trigger are being integrated

  4. Trigger Processor block diagram

  5. Pixel Processor and Segment Tracker (PP&ST) • BB33 algorithm is being implemented in VHDL code (Ted, Ken) • Inner and outer doublets • Objectives: • Obtain better processing time estimates • Determine silicon requirements • Optimize algorithm implementation based on the size-speed tradeoff • Some simulations to improve BB33 algorithm implementation (Vince) • Alternatives to speed-up PP&ST processing or reduce silicon size

  6. Pixel Processor and Segment Tracker (PP&ST) (2) • Data flow analysis: Queuing analysis and simulation (Gustavo) • Data flow models have been developed • Some good suggestions like N-way branching (highways) • Buffer sizes, data channel speed. • Behavioral simulations are underway • closely related to VHDL implementation

  7. Pixel HS Pixel HS . . . . . . Pixel front-end(DCB) Pixel front-end(DCB) N-way branching N-way branching Segment processor Segment processor Segment processor Segment processor Segment processor #1 Segment processor #1 Switch Switch Switch Track & Vertex Processor Track & Vertex Processor Track & Vertex Processor Track & Vertex Processor Track & Vertex Processor Track & Vertex Processor Track & Vertex Processor Track & Vertex Processor Track & Vertex Processor Trigger Processor N-way branching • Advantages of N-way branching (highways): • Data uniformly distributed in fiber channels • Increase budget time of the Segment Processors • Chance to test several trigger algorithms at the same time • Fault tolerance • Supervise highway performance

  8. DSP Farm Prototype board • Motherboard will have up to 4 Texas Instrument DSPs • Mezzanine DSP cards will allow testing of more than one typeof DSP. Floating point and fixed point DSPs will be supported. • DSP Farm Prototype main features: • PTSM (Pixel Trigger Supervisor & Monitor) network connection • Input and output ports to PCI-based Test Stand • Local memory for Segment Data • JTAG interfaces for programming • On-board microcontroller for network data handling and statistics • Test goals • study hardware constraints (i.e. DMA access, communication ports, FPGA and memory bandwidths, etc) • DSP algorithms and kernels • hardware-software integration

  9. DSP Farm Prototype board (2)

  10. Other Trigger Tasks • PTSM (Pixel Trigger Supervisor & Monitor) (Greg, Vince) • Specification of network • Specification of interfaces and protocols • DSP farm (Erik, Vince, Xiaonan, David, Mike H, Mike W.) • Analysis and Specification of DSP farm • DSP test boards • DSP software • Trigger algorithms (Erik, Mike W.) • Generation of track-segment data (triplets) to feed DSPs • NSF ITR Proposal (Erik, Vince) • Request for funding for work on fault tolerance along with related DSP hardware and software issues.

  11. The Near Future • Prioritize tasks for the BTeV Technical Design Report for February 2002. • More work on WBS, dictionary, and costing • DSP simulations • DSP line will probably be defined • more accurate estimation of computational time required • Data flow analysis • PTSM prototype • BB33 fully implemented in VHDL • possible improvements in the segment finder algorithm

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