MINOS Readout Schematic

1. MINOS Readout Schematic 16 ch PMT’s PMT 3 1 1 3 3 1 3 1 Front End Electronics HV FEB HV FEB FEB FEB Front-end Board 12 FEBs Readout Board ROB ROB ROB ROB ROB ROB 3 2 1 VME VME 2.5 MB/s Readout Processor Readout Crates ROP ROP Timing RC Timing RC DAQ LAN DAQ LAN PVIC PVIC 16 1 10 Mbytes/s PVIC bus 4 1 B R P B R P B R P B R P Timestamp Clock 1 sec GPS ticks DAQ LAN Readout Control antenna Data Distribution System 40 Mbytes/s PVIC bus DAQ LAN DAQ LAN Timing Central unit GPS SNTP PC Trigger Processors TP TP TP PC To store n 2 1 10-100 Kbytes/s Central Clock System

2. Far Front-end Electronics Linearity • Number of pe reconstructed from read out data • Good Linear response • Requirement: 5%

3. Data Transfer Rates • Readout rate of Far front-end readout to VME processor • Achieved 5x required rate Transfer Rate (MB/s) Required Size of Transfer (bytes)

4. Far Front-end response

5. Far Front-end: Timing Resolution • Test with delay cables • Using FPGA • Achieved expected 1.5ns timing resolution Time bin measured Pulse Delay (ns)

6. Far Front-ends Digitizing board • Readout board prototype Front-end board VME interface, sparsifier,buffer

7. Electronics/DAQ Vertical Slice at RAL Scint. Mini-module with Light Injection Prototype (LED) pulser box Branch Readout & Trigger farm PC’s VME crate: VA readout controller, timing receiver card, readout processor High Voltage System (LeCroy) MUX box and front-end board

8. Near Electronics: Linear Response 1 MIP

9. Near electronics: Residual from Linear 10 fC (Equiv. to 0.2 pe) 1%