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Tilecal VFE developments at Clermont-Ferrand June 2010 Status G Bohner, J Lecoq, X Soumpholphakdy

Tilecal VFE developments at Clermont-Ferrand June 2010 Status G Bohner, J Lecoq, X Soumpholphakdy F Vazeille, D Pallin. One VFE ASIC for Tilecal. VFE ASIC design : see February TILE week J Lecoq talk http://indico.cern.ch/conferenceDisplay.py?confId=84640 Specifications

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Tilecal VFE developments at Clermont-Ferrand June 2010 Status G Bohner, J Lecoq, X Soumpholphakdy

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  1. Tilecal VFE developments at Clermont-Ferrand June 2010 Status G Bohner, J Lecoq, X Soumpholphakdy F Vazeille, D Pallin DPallin sLHC_Tile meeting

  2. One VFE ASIC for Tilecal • VFE ASIC design : • see February TILE week J Lecoq talk http://indico.cern.ch/conferenceDisplay.py?confId=84640 • Specifications • Large dynamic range, 16 to 17 bits • Tilecal signal : 5 ns rise time , 40 ns fall time. • Least significant charge: 25 fC • Most significant charge: 0.8 nC (1 to 1.2 nC ?) • The noise (and LSB) is half part of the smallest signal (12,5 fC) • The corresponding maximum currents are: • Minimum (1 LSB) of 625 nA • Maximum (full scale) 40 (60 mA ?) • => multi gain: 3 in this study ( 1, 8, 64) DPallin sLHC_Tile meeting 2

  3. General design Shaper ADC Shaper Current conveyor PMT Shaper The base line is a current conveyor with 2 or 3 gains, shaper RC and ADC To stay in a current mode (don't convert in voltage). To provide multigains => To duplicate currents. Next stages in Voltage mode. A version with a passive shaper before the conveyor like in tile VFE has been simulated also. Then the only difference is the way to split the signal to get a multigain. Now R&D only for conveyor in IBM 130 nm. DPallin sLHC_Tile meeting

  4. conveyor layout • Run IBM 130nm via CERN sent in foundry may 2010 • Some extra delay at CERN • => Tests of the produced conveyor in September 2010 1mm x 135µm DPallin sLHC_Tile meeting

  5. Simulation results • With a very simple shaping on each gain ( at 40ns peaking time) • Results on linearity shown during last meeting • G64 50V/1V=5 10-5 ; G8 500V/1V=5 10-4 ; G1 20mV/1V=2 10-2 • Now studies on the impact of the VFE resolution to the overall detector jet resolution Unipolar Shaping Peaking time 40 ns. Signal after shaping Linearity DPallin sLHC_Tile meeting 5

  6. Simulation results • Studies on the impact of the VFE resolution on jet resolution • Noise on VFE • TILE VFE+ADC noise+OF G64 G1 • Noise on ADC VFE LPC (10bit ADCs) • Overestimated assumption : ½ LSB • Next time : ADC noise simulation using observed noise on comparators DPallin sLHC_Tile meeting 6

  7. Simulation results • Studies on the impact of the VFE resolution on jet resolution • Conversion charge to Energy • From - for jets use 0.9 pC/GeV. - for muons 1.15pC/GeV VFE Clermont 3 gains (64 8 1) 10 bit ADCs DPallin sLHC_Tile meeting 7

  8. Simulation results VFE Clermont 3 gains (64 8 1) 10 bit ADCs DPallin sLHC_Tile meeting 8

  9. Simulation results VFE Clermont 2 gains (64 1) 10 bit ADCs DPallin sLHC_Tile meeting 9

  10. Simulation results • 8 bits ADC not adequate to resolve muons with required S/N • 10 bits ADC / 2 gains (64,1) within specifications • Lower impact than tile electronics on jet resolution ( with crude assumption on ADC noise and no OF) • 10 bits ADC / 3 gains (64,8,1) much better as expected • Very good linearity • No problem to provide 3 gains in conveyor configuration • Even better if gain choice is (64, 4,1) DPallin sLHC_Tile meeting 10

  11. Conclusions Noise and linearity performances reach all the specifications. VFE Tests in september. Amplifier R&D : study going on. Simulation of sampling + OF and « real ADC » noise going on What is the best peaking time to choose ? Simulation showed that a better S/N is obtained with a peaking time of 25ns. 10 bits ADC / 3 gains (64,4,1) is the best compromise from fast simu. Is Tile community in favour of a 3 gains configuration ? If not: why ? DPallin sLHC_Tile meeting

  12. BACKUP SLIDES DPallin sLHC_Tile meeting

  13. Why a current conveyor? The signal delivered by the PMT is a current. Its conversion to a voltage is easy: With a simple impedance (resistor and/or passive shaper) U=Zi The multi gain is easy to achieve. BUT: The output impedance is Z ! => Open door for the noise, the crosstalk and the bandwidth ! Z With an amplifier, U=Zi again BUT: the impedance seen from the PMT is divided by the amplifier gain (now Z/Av). Reduction of the noise and crosstalk. The bandwidth is only given by the amplifier. A multi gain is impossible on this stage. The dynamic range is poor. Z Av 8 février 2010 DPallin sLHC_Tile meeting Jacques Lecoq, réunion atlas LPC 13

  14. Results with a very simple shaping on each gain Adding a simple shaping at 40 ns peaking time: (Only RC here, could Be adapted to CR-RC) Current from the current conveyor DPallin sLHC_Tile meeting 14

  15. The current conveyor solution The idea: Stay in current mode (don't convert in voltage). we need an input impedance as low as possible, an output impedance as high as possible, the possibility to handle a multi gain at the first stage. To do this copying current is sufficient: A common gate architecture is simple and efficient … 8 février 2010 DPallin sLHC_Tile meeting Jacques Lecoq, réunion atlas LPC 15

  16. With a current conveyor: The advantages are: The multi gain is free, less gains are simply given by par the transistor scales . (W/L). Le current increase like the signal : The quiescent current could be low. With submicron MOS gm too small: The output impedance 1/gm is not small enough. 8 février 2010 DPallin sLHC_Tile meeting Jacques Lecoq, réunion atlas LPC 16

  17. The « super » current conveyor • The input is a “super common gate”. • Vi is fixed by a feedback loop. • The input impedance become 1/(gm0*gm3*R6) • More: • This architecture is self polarized. • The current is twice copied. • The quiescent current is small (only 1 mA for • a signal current up to 50 mA or more.) • The input impedance is now very low. • It is easy to obtain a differential structure. 8 février 2010 DPallin sLHC_Tile meeting Jacques Lecoq, réunion atlas LPC 17

  18. Simplified (2 gains) diagram in IBM 130nm Differential structure. Multi gain by current copy 3 gains, ratio 1, 8, 64 0-625 µA (high gain) 625µA-5mA (medium) 5-40mA (small gain) PM This correspond in fact to: 1,75k Ω, 217 Ω et 25 Ω. 8 février 2010 DPallin sLHC_Tile meeting Jacques Lecoq, réunion atlas LPC 18

  19. OUT1 PMT OUT8 Convoyer : schematic differential stucture gains with current mirrors 3 gains (1, 8, 64) : 0 to 625µA (800 µA) 625µA to 5mA (6.4mA) 5mA to 40mA (5.1mA) DPallin sLHC_Tile meeting

  20. Simulation results linearity Input impedance versus magnitude 1 Ω 40mA VFE pour Tilecale 40mA Input impedance versus frequency 2.34 Ω DPallin sLHC_Tile meeting 1kHz 10MHz

  21. The noise (worse case, after shaping) Noise on the highest gain: 500µV, 0.5 LSB 8 février 2010 DPallin sLHC_Tile meeting Jacques Lecoq, réunion atlas LPC 21

  22. Simulation results after shaper Shaper : 5kΩ 20pF (40ns) linearity Gain 8 : ± 500µV Gain 64 : ± 50µV Gain 1 : ± 20mV 1V 1V 1V out noise Gain : 64 σ = 500µV 1/2 LSB 0.22 10-6 DPallin sLHC_Tile meeting

  23. One amplificator prototype Design : only one stage, folded cascoded DPallin sLHC_Tile meeting

  24. Amplificator simulation DPallin sLHC_Tile meeting

  25. Amplificator layout Run IBM 130nm via CERN sent in foundery mai 2010 370µm x 670µm DPallin sLHC_Tile meeting

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