WP2: on-detector power management

1. WP2: on-detector power management F.Faccio, G.Blanchot, S.Michelis, S.Orlandi, C.Fuentes, B.Allongue CERN – PH-ESE

2. Outline • Introduction • Project structure • Working Team • Communication • Composition of WP2 • Technical status • WP2-1 • WP2-2 and 2-3 • Resources • Conclusion CERN - PH dept – ESE group

3. No on-detector conversion. Low-voltage (2.5-5V) required by electronics provided directly from off-detector. Sense wire necessary for PS to provide correct voltage to electronics. Patch Panels (passive connectors ensuring current path between different cables. Regulation is very seldom used) PS Current path from PS to module (or more seldom star of modules) and return. Cables get thinner approaching the collision point to be compatible with material budget. Distributing power CERN - PH dept – ESE group

4. Distributing power CERN - PH dept – ESE group

5. 10xV, I V, 10xI DC-DC I 1xI 10xV Distributing power with DC-DC • The use of DC-DC converters allows the distribution of the power at higher voltage, while the converters provide locally the voltage level(s) required by the electronics DC-DC principle Principle distribution scheme CERN - PH dept – ESE group

6. Challenges • Converters to be placed inside the tracker volume Magnetic field (up to 4T) Radiation field (>10Mrd) Environment sensitive to noise (EMI) • Commercial components are not designed for this radiation and magnetic environment, we need a custom development (ASICs) • Space is very limited, and requirements for low mass stringent. High level of integration is mandatory • Our goal: develop the ASICs necessary for the power distribution, and help their integration in full detector systems CERN - PH dept – ESE group

7. Outline Introduction Project structure Working Team Communication Composition of WP2 Technical status WP2-1 WP2-2 and 2-3 Resources Conclusion CERN - PH dept – ESE group

8. The team CERN - PH dept – ESE group

9. Communication and coordination • In opposition to the early R&D phase of LHC, power distribution is today very fashionable • 3 Working Groups: ATLAS, CMS, “common” • CMS task force (first meeting today) • Separate sessions at TWEPP, ATLAS and CMS upgrade workshops, ACES • SLHC-PP within FP7 • Parallel activities on other distribution schemes (serial powering) or different conversion approaches exist • Expectations of the community are high (and impatient – maybe unnecessarily…) • This all puts the development under constant pressure – and requires a very large amount of energy in reporting, coordination, discussions, …. • Our activity is well known and reasonably well integrated in both ATLAS and CMS – and improving CERN - PH dept – ESE group

10. Composition of WP2 • Time frame: 3 years • Split of the project in 3 parts • WP2-1: Linear voltage regulation • Development of “stand-alone” component for low current (100-300mA) applications • WP2-2: DC-DC conversion (corresponding to SLHC-PP deliverables) • Development of converter prototype, integration in full-scale detector modules • WP2-3: DC-DC conversion, Addition • Aspects and activities not covered by SLHC-PP CERN - PH dept – ESE group

11. Outline Introduction Project structure Working Team Communication Composition of WP2 Technical status WP2-1 WP2-2 and 2-3 Resources Conclusion CERN - PH dept – ESE group

12. WP2-1: Status • Deliverables: • Progress: • Full schematic of the main regulation loop ready in IBM 130nm CMOS • Protection circuits (over-V, over-I, over-T) almost complete in schematic • The component does not look to be really needed now. Much more pressure on DC-DC development • To be discussed at technical committee meeting (December?) CERN - PH dept – ESE group

13. WP2-2 and 2-3: deliverables • WP2-2 Deliverables (in parenthesis also WP2-3) : • Specific Additions in WP2-3 • Consultancy to procure expertise in power electronics • Transformer based on piezoelectric ceramic materials • Second source CMOS technology • Optimization of air-core inductor CERN - PH dept – ESE group

14. Evaluation of conversion technologies • Consultancy relationship established with PEL (Power Electronics Labs), University of Padova • This collaboration proved extremely valuable • 2 reports already produced. Design of 2 converters executed and first prototype manufactured • Comparison of 5 different converter topologies taylored for our specific application. Choice restricted to 2 topologies (simple buck and 2-phase interleaved buck with voltage divider) • Results from the measurements of the 2 converter prototypes (discrete components) • 4 common working sessions organized: 2 in Padova and 2 at CERN (2-3 days each) • Extremely efficient form of transfer of knowledge • Large progresses in the project • Outcome: we proposed at TWEPP a power distribution scheme for SLHC trackers CERN - PH dept – ESE group

15. Proposed power distribution scheme 10-12V If Ihybrid<< Iout_converter If Ihybrid~ Iout_converter 2 Converter stage2 on-chip 2 Converter stage 2 on-chip 10-12V Detector Detector 2.5V 1.8V Detector 2.5V 1.8V Converter stage 1 2.5V Detector 1.8V 2.5V 1.8V 2.5V Optoelectronics 1.25V Stave controller Converter stage 1 on-hybrid 10-12V Converter stage 2 10-12V Converter stage 1 on-stave Rod/stave CERN - PH dept – ESE group

16. Different converter topologies (1/3) The following DC/DC step down converter topologies have been evaluated and compared in view of our specific application. • Single phase synchronous buck converter • Simple, small number of passive components • Larger output ripple for same Cout • RMS current limitation for inductor are output capacitance • 4 phase interleaved synchronous buck converter • Complete cancellation of output ripple for a conversion ratio of 4 (with small Cout) • Smaller current in each inductor (compatible with available commercial inductors) • Large number of passive components • More complex control circuitry L1 Vin Vout Q1 Rload Q2 Cout L1 Vin Vout Q1 Q2 L2 Rload Cout Q3 Q4 L3 Q5 Q6 L4 Q7 CERN - PH dept – ESE group Q8

17. i g Q 1 i C r 1 Q I L 2 o r V g + D v C 1 r + r v Load C o 2 D 2 Different converter topologies (2/3) • Two phase interleaved synchronous buck converter with integral voltage divider • Complete cancellation of output ripple for a conversion ration of 4 (with small Cout) • Simpler control and smaller number of passive components than 4 phase interleaved • Multi-resonant buck converter • Very small switching losses (zero voltage and zero current switching) • To achieve resonance: • Current waveforms have high RMS value => large conductive losses => lower efficiency • Voltage waveforms have high peaks, possibly stressing the technology beyond max Vdd • Different loads require complete re-tuning of converter parameters CERN - PH dept – ESE group

18. i g Q + 1 i C x 1 Q I 2 o + V v g x C Q x 3 + v Load C o 2 Q 4 Different converter topologies (3/3) • switched capacitor voltage divider • rather simple , limited number of passive components • lack of inductor => good for radiated noise and for compact design • No regulation of the output voltage, only integer division of the input voltage • Efficiency decreases with conversion ratio (larger number of switches) • Good solution for ratio = 2, for which high efficiency can be achieved CERN - PH dept – ESE group

19. Conversion stage 1: topology Waveforms of the different topologies have been computed with Mathcad, and conversion losses have been estimated for each of them in the same conditions: Vin= 10V, Pout= 6W, Vout= 2.5V (step down ratio = 4), use of AMS 0.18um technology with approximate formula to account for switching losses The best compromise in terms of efficiency, number of components required, complexity and output ripple is the 2 phase interleaved buck with integrated voltage divider. CERN - PH dept – ESE group

20. Implementation: conversion stage 1 • The final result of our study is that, for the development of a unique ASIC conversion stage 1 for both analog and digital power distribution, the best solution is: • 2-phase interleaved buck with integrated voltage divider • Switching frequency = 1 MHz • On-resistance of switching transistors = 30 mW • The inductor can be chosen for the specific output current wished in the application, achieving the efficiency estimated in the graphs below for the AMS 0.18 technology (Coilcraft RF 132 series inductors are used) DIGITAL, Vout=1.8V ANALOG, Vout=2.5V CERN - PH dept – ESE group

21. Implementation: conversion stage 2 Vin Q1 Q2 Vout=Vin/2 Q3 Q4 gnd • Two converters to be embedded on each chip • Output current rather modest (20-200 mA) • Inductor-based converters not envisageable: • With on-chip inductors (high ESR) the efficiency would be extremely low • The use of several discrete inductors per ASIC is not desirable – already only for system integration purposes • Switched capacitor converters more suitable • Acting as voltage divider (÷2) • They unfortunately do not provide regulation, which must be relied on from conversion stage 1 • Achievable efficiency has been estimated, then refined with a quick simulation in a 130nm technology (use of I/O transistors) • Efficiency (Vin=1.8V, Vout=0.9V, Iload=166mA, f=20MHz) = 93% • It should be pointed out that no study on the optimization of this converter has been made – one only topology, with one fixed frequency has been studied (efficiency can be improved further by decreasing the frequency, for instance). CERN - PH dept – ESE group

22. WP2-2 and 2-3: deliverables • WP2-2 Deliverables (in parenthesis also WP2-3) : • Specific Additions in WP2-3 • Consultancy to procure expertise in power electronics • Transformer based on piezoelectric ceramic materials • Second source CMOS technology • Optimization of air-core inductor CERN - PH dept – ESE group

23. Prototype of converters • Several prototype converters using discrete components have been manufactured • Main objective: study EMC • First integrated prototype developed and manufactured in a CMOS 0.35um technology with high-V module CERN - PH dept – ESE group

24. ASIC development • ASIC designer: Stefano Michelis • Prototype for “conversion stage 1” • First prototype designed and manufactured in AMIS I3T80 technology • Simple buck topology • Vin up to 10V • Vout=2.5V • Iout up to 1.5A • switching frequency 0.3-1.2 MHz • ASIC included main functions only (switches, control circuitry) • External compensation network, reference voltage and sawtooth generator required CERN - PH dept – ESE group

25. ASIC Prototype performance • ASIC mounted on a custom PCB (chip on board) • Functionality is OK, it provides regulated output at 2.5V for different loads • Efficiency limited to 70% max. • Known limitations from the use of vertical transistors with large Ron • Additional losses probably due to “shoot-through” (verification ongoing) • Noise performance very reasonable • Used already to power CMS endcap tracker modules (RWTH Aachen) • Second version – more complete and with different power transistors – to be submitted at the beginning of December CERN - PH dept – ESE group

26. WP2-2 and 2-3: deliverables • WP2-2 Deliverables (in parenthesis also WP2-3) : • Specific Additions in WP2-3 • Consultancy to procure expertise in power electronics • Transformer based on piezoelectric ceramic materials • Second source CMOS technology • Optimization of air-core inductor CERN - PH dept – ESE group

27. CMOS technology • Full radiation characterization of AMIS IT380 technology (0.35um CMOS) completed • Report available • Performance not really matching requirements • Contacts established, in synergy with WP1, with two alternative providers • STM, possibly interested to a common development. 2 of their technologies selected, samples provided. Samples are being irradiated now • AMS, developing a new 0.18um high-V CMOS technoloogy with IBM. Participation in first MPW confirmed, but delayed by 6 months to 4/09 • Contacts established with another alternative supplier, IHP • Contact established via CNM Barcelona (ATLAS), now in coordinated way with RTWH Aachen (CMS) • Provided samples are being irradiated now • IHP willing to collaborate in enhancing and maintaining radiation hardness • Design of test chip in collaboration with CNM and IHP is in progress • Objective: select one technology with appropriate characteristics, and move ASIC prototyping in that technology as soon as possible CERN - PH dept – ESE group

28. WP2-2 and 2-3: deliverables • WP2-2 Deliverables (in parenthesis also WP2-3) : • Specific Additions in WP2-3 • Consultancy to procure expertise in power electronics • Transformer based on piezoelectric ceramic materials • Second source CMOS technology • Optimization of air-core inductor CERN - PH dept – ESE group

29. Optimization of air-core inductors • Inductors are crucial components for the converter • Air-core inductors have to be used since ferromagnetic materials saturate in the high magnetic field of CMS/ATLAS • Since the current flowing is not dc, they are emitters of magnetic field. This can induce noise • Their parasitic resistance strongly influences efficiency • Simulation studies are made to compare magnetic field and ESR of different inductor designs • After choice of design, prototypes have to be manufactured • This will likely require establishing relationship with industry (custom coil manufacturers), unless a planar PCB solution is chosen CERN - PH dept – ESE group

30. Which inductor to use? • Air-core inductors can be manufactured in different configurations (planar, solenoidal, thoroidal, ….) and a choice should be made • Value: reasonably limited in range 100-700nH • Equivalent resistance (ESR) determines converter efficiency to sensible extent Planar (on PCB) Solenoidal Thoroidal ESR~100mW ESR~20-30mW ESR~20-30mW CERN - PH dept – ESE group

31. Air core solenoid Not shielded Shielded Value @ 11mm far from the solenoid: 5µT 18nT CERN - PH dept – ESE group

32. Air core toroid Value @ 11mm far from the toroid: 6.6µT CERN - PH dept – ESE group 11mm far from the centre of the toroid

33. Example PCB Toroid This PCB toroid was developed at Bristol, Aknowledegment to David Cussans Not shielded Shielded Value @ 11mm far from the toroid: 19µT 70nT CERN - PH dept – ESE group

34. WP2-2 and 2-3: deliverables • WP2-2 Deliverables (in parenthesis also WP2-3) : • Specific Additions in WP2-3 • Consultancy to procure expertise in power electronics • Transformer based on piezoelectric ceramic materials • Second source CMOS technology • Optimization of air-core inductor CERN - PH dept – ESE group

35. Integration in detector modules • Main issues for integration: EMC and physical space • EMC • Measurements of noise (conducted and radiated) on converter prototypes • Module-level tests • @ RWTH Aachen with CMS TEC modules • @ CERN with TOTEM Si Strip modules CERN - PH dept – ESE group

36. Conducted noise measurement Reference test bench developed within ESE Well defined measurement methods for reproducible and comparable results. Independence from the system and from the bulk power source. Arrangement of cables, input and output filter (LISN) around the converter under test, all above a ground plane. CERN - PH dept – ESE group

37. Noise measurement on different CERN prototypes All the measurement were made in these conditions: Vin=10V, Vout=2.5V, Iout=1A and fsw=1Mhz Proto 1,2,3 were developed at CERN with the same controller. PCB layout and parasitic component choice was improved Proto 4’s PCB was designed in Aachen and the ASIC (in the red spot) was designed at CERN Proto2 ~58dBµA ~62dBµA Proto1 Proto4 Proto3 ~51dBµA ~46dBµA CERN - PH dept – ESE group

38. TOTEM Front-End system supplied with DC-DC converters Powering a detector module Expose the front-end system to the DC-DC converter conducted noise (Common Mode and Differential Mode currents) CERN - PH dept – ESE group

39. WP2-2 and 2-3: deliverables • WP2-2 Deliverables (in parenthesis also WP2-3) : • Specific Additions in WP2-3 • Consultancy to procure expertise in power electronics • Transformer based on piezoelectric ceramic materials • Second source CMOS technology • Optimization of air-core inductor CERN - PH dept – ESE group

40. Piezoelectric transformers • 2-days workshop organized in April at CERN • Held with Limiel (Dk) – consultancy firm on piezoceramic materials and (in particular) their applications • Nothing similar to what we would need exists – requirement for developing both the custom ceramic device AND the driving circuitry • No on-field reliability data exist!! • Further difficulties emerged during the workshop • Need for an output rectifier (difficult to achieve high efficiency for low voltage) • Since the capacitance of the transformer has to be matched to the load, its size gets unpractical in our application (several cm per side, very thin) • The transformer can not cope with sudden output open – too much energy stored that can not be dissipated. This is a safety concern • Conclusions • It looks very unlikely that an attractive solution for our application can be found • In any case, an activity aimed purely at demonstrating the feasibility of such very innovative approach would require our full resources • We decided to abandon this solution CERN - PH dept – ESE group

41. Outline Introduction Project structure Working Team Communication Composition of WP2 Technical status WP2-1 WP2-2 and 2-3 Resources Conclusion CERN - PH dept – ESE group

42. Resources Funds Manpower • Very good, young and motivated team. Experience acquired through consultancy • Size adequate (addition of 1 fellow in mid-09) • 1 staff LD crucial to ensure continuity of the project (main designer is MC fellow) CERN - PH dept – ESE group

43. Conclusion • Excellent progress in the first months of activity • Work started also on deliverables for 2011! • WP activity well on-budget • Activity focused on DC-DC converters – following demand from the experiments • If appropriate continuity is ensured in terms of manpower and funds, WP2 will provide a viable solution for the SLHC experiments CERN - PH dept – ESE group