1 / 12

paper I

paper I design and implementation of the aegis single-chip secure processor using physical random functions, isca’05 nuno alves 28/sep/06. paper about? new computer architecture for secure computation what’s interesting? use of manufacturing process variations to generate random numbers.

libra
Download Presentation

paper I

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. paper I design and implementation of the aegis single-chip secure processor using physical random functions, isca’05 nuno alves 28/sep/06

  2. paper about? new computer architecture for secure computation what’s interesting? use of manufacturing process variations to generate random numbers introduction

  3. why? identify a computer why do we need random numbers in a computer architecture? encrypt and decrypt sensitive information verify and validate the source

  4. generating random signals always 1 output 1 if top signal is faster inputs conclusion: process variations prevent output to be always the same

  5. paper II making typical silicon matter with razor. ieee proc’04. nuno alves 28/sep/06

  6. paper about? architecture for safely scaling down voltage tradeoffs: energy  = vdd  = performance  clock frequency  = vdd  introduction

  7. voltage scaling • reduce voltage for period of low processor utilization • there is a minimum required voltage

  8. determining worst case scenario slow, but always right, multipliers start decreasing vdd fast multiplier = slow multiplier?

  9. results 98.7% accurate here that’s like… 1 error in every 1.8 billion operations No errors at 85 No errors at 27

  10. detecting infrequent errors same as main flip-flop but delayed

  11. correcting infrequent errors error detected, stall clock

  12. this architecture : eliminates voltage margins associated with variations between different chip instances helps with gamma rays and alpha particles mitigating reliability and variability problems

More Related