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FPGA Design Using the LEON3 Fault Tolerant Processor Core

FPGA Design Using the LEON3 Fault Tolerant Processor Core. Jiri Gaisler and Sandi Habinc. Outline. Introduction Fault tolerant LEON3 processor Design environment Design flow Results Validation Projects and availability Lessons learned. Introduction.

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FPGA Design Using the LEON3 Fault Tolerant Processor Core

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  1. FPGA Design Using the LEON3 Fault Tolerant Processor Core Jiri Gaisler and Sandi Habinc

  2. Outline • Introduction • Fault tolerant LEON3 processor • Design environment • Design flow • Results • Validation • Projects and availability • Lessons learned

  3. Introduction • High density FPGA devices are now large enough to support SOC design for space application • This allows completely new applications to be implemented in FPGAs, which have previously been limited to ASICs • One problem however remains the same: How to implement fault tolerant processor based SOC designs?

  4. Common design issues • Processor availability issues: • Component obsolescence, export licenses etc. • Space application issues: • SEU protection or hardening • System integration issues: • Harmonisation of interfaces (on-chip buses) • Mapping of technology specific cells (RAM) • Software environment issues: • Operating system support

  5. LEON3 SPARC V8 Processor • Advanced 32-bit processor IP core implementing the SPARC V8 standard instruction set • 7-stage pipline, hardware mul/div • Separate instruction and data multi-set caches • Multi-processor support (up to 16 processors) • On-chip debug support unit for: • Non-intrusive hardware debugging • Instruction trace buffer • On-chip bus trace buffer

  6. LEON3 SPARC V8 Processor (cont.) 3-Port Register File IEEE-754 FPU 7-stages Integer pipeline Trace Buffer Co-Processor Debug Support Debug Support Unit HW Mul/Div Interrupt Port Interrupt Controller Local I-RAM I-Cache D-Cache Local D-RAM AHB Master I/F AMB AHB Master (32 bit)

  7. LEON3 Fault Tolerant Processor • SEU tolerance by design for space applications • All on-chip memory protected against SEUs: • 136x32 bit register file: 4-bit parity and duplication • Cache RAMs use 4-bit parity and forced cache miss on error • No timing penalty • Instruction re-scheduling on error • Flip-flops assumed to be protected by technology specific cells (or by TMR)

  8. LEON3 design environment • LEON3 is part of a complete design environment: • Floating Point Unit, Mul/Div • Timers, Interrupt Controller, • Memory controllers (SRAM, SDRAM) • SpaceWire, CAN, Ethernet, PS2, UART, PCI, MIL-STD-1553B • CCSDS Telemetry/Telecommand • AMBA on-chip bus with new Plug and Play support • Support for many tools and prototyping boards • Support for portability between technologies

  9. Typical design flow • Download LEON3 source code from the web • Modify design example by adding design blocks • Simulate using one of many simulators(several simulators supported, one free) • Synthesize using one of many tools(several tools supported, some free) • Place and route FPGA using vendor specific tools(several FPGA vendors supported, some free) • Target design to one of many development boards (several boards supported)

  10. Fault Tolerant design flow • Modify LEON3 design example by adding additional design blocks • Synthesize and place and route design (e.g. free Xilinx XST web-pack or Altera Quartus web-pack) • Validate the design on your prototype board • This complete initial flow is based on the non-FT version of LEON3

  11. Fault Tolerant design flow (cont.) • Synthesize design, using e.g. Synplify, targeting Actel RTAX-S • Place and route design using Actel Designer, including the LEON3-FT EDIF netlist • Validate the design on your enginering or flight board • The only thing changed is the LEON3-FT core

  12. RTAX2000S development • The GR-CPCI-AX prototyping board was developed for AX2000 and RTAX2000S devices • Initial example design successfully validated: • LEON3 • PCI master/target • Memory Controller • Interrupt Controller

  13. RTAX2000S results – LEON3 • LEON3-FT, 8 + 8 kbyte cache • 7,500 cells (24%) + 40 of 64 RAM blocks, (or 22,000 ASIC gates + RAM) • LEON3-FT, 8 + 8 kbyte cache + DSU3 • 8,500 cells (27%) + 40 of 64 RAM blocks,(or 27,000 ASIC gates + RAM)

  14. RTAX2000S Results – Memory • SRAM controller: FTSRCTRL • 600 cells (2%), (or 2,000 ASIC gates) • SDRAM controller: FTSDCTRL • 900 cells (3%), (or 3,000 ASIC gates) • On-chip memory: FTAHBRAM (2 Kbyte EDAC) • 300 cells (1%) + 5 of 64 RAM blocks,(or 2,000 ASIC gates + RAM)

  15. RTAX2000S results – Others • GRFPU-Lite-FT including LEON3 controller: • 7,100 cells (23%) + 4 of 64 RAM blocks • SpaceWire-FT link: • 2,800 (9%) + 5 of 64 RAM blocks

  16. RTAX2000S results – Example designs App 1: App 2: App 3: App 4: LEON3-FT LEON3-FT LEON3-FT LEON3-FT DSU DSU GRFPU-Lite-FT IRQ/UART IRQ/UART IRQ/UART IRQ/UART FT-SRAM FT-SRAM FT-SRAM FT-SDRAM SPW-FT SPW-FT 35% cells 38% cells 45% cells 75% cells 40 of 64 RAM 40 of 64 RAM 45 of 64 RAM 49 of 64 RAM 25 MHz 25 MHz 25 MHz 25 MHz

  17. Validation • LEON3 has passed SPARC V8 validation • AX2000 based design running since 2005Q2 • RTAX2000S based design planned for 2005Q3 • Software induced SEU testing on-going • Radiation testing planned for 2005Q3: • Heavy Ion • Californium • Louvain-la-Neuve • Proton

  18. Projects • LEON3-FT processor being evaluated in the frame of the European spacecraft Bepi-Colombo • To be used in 5-10 different instruments as primary controller • Includes SpaceWire interface and Floating Point Unit • LEON3-FT processor is on the road map for the European Space Agency, replacing the LEON2 processor

  19. LEON3 Availablity • Freely available in source code under GNU GPL • Valuable tool for academic research • Improves test-coverage due to large user-base • Allows early prototyping and try-before-buy • Commercial licensing possible without restrictions • The fault-tolerant version of the coresarenot initially released in open-source, but the long-termstrategy is to release all cores under GPL

  20. Lessons learned • Fault tolerance implementation differs between ASIC and FPGA: • The critical timing paths for ASIC and FPGA differs, forcing different FT implementations • FPGAs have fixed on-chip resources that can be used for FT implemenation without additional area penalty • Mixed GPL and commercial licensing model necessary to allow both academic and commercial use

  21. Conclusions • LEON3 Fault Tolerant SPARC processor core is ready for FPGA /ASIC integration, including: • SEU protection • Design environment with several cores • Development board for RTAX and AX • RTAX2000S with LEON3-FT leaves ample space for customer specific logic and memory: • Cells: 25% to 65% (up to 60k ASIC gates) • RAM: 24% to 37% (up to 100k bits)

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