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2010. 08. 10 Changkun Park

ETRI 위탁연구과제 Power Amplifier 중간 발표. 2010. 08. 10 Changkun Park. Introduction. Strategy for CMOS PA. Characteristics of CMOS. Problems. Solutions. Goal. Low breakdown voltage. Low output power. Cascode structure. High efficiency CMOS PA. Lossy substrate. Low efficiency.

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2010. 08. 10 Changkun Park

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  1. ETRI 위탁연구과제 • PowerAmplifier 중간 발표 • 2010. 08. 10 • Changkun Park

  2. Introduction

  3. Strategy for CMOS PA Characteristics of CMOS Problems Solutions Goal Low breakdown voltage Low output power Cascode structure High efficiency CMOS PA Lossy substrate Low efficiency Voltage combining method No via process Gain reduction Differential structure

  4. Voltage Combining Technique Current combining technique • Hard to implement output matching on a chip • Sensitive matching network Voltage combining technique • Impedance transformation • Low losses Ref : I. Aoki et al, “Distributed active transformer,” T-MTT, Jan. 2002.

  5. Power Amplifier - Conventional Simplified Schematic Characteristics • Power Stage • Class AB • 2-Differential Pair • TLT for Matching Network • Cascode structure • Driver Stage • Class AB • 1-Differential Pair • Spiral Transformer • Cascode structure

  6. Power Amplifier - Conventional

  7. Power Amplifier – with 3-port TLT Simplified Schematic 3-port Transformer • Multi-primary structure • Dual load impedance

  8. Power Amplifier – with 3-port TLT Impedance transformation using transmission line transformer

  9. Power Amplifier – with 3-port TLT Impedance transformation Assume RT = 25 Ω k-factor = 0.5 • L1 increase  High RLOAD • L1 decrease  Low RLOAD • L1 can be changed by • Length • Width • Structure

  10. Power Amplifier – with 3-port TLT Layout Characteristics • Power Stage • Class AB • 2-Differential pair • 3-port TLT for output matching • Cascode structure • Driver Stage • Class AB • 1-Differential Pair • Spiral Transformer • Cascode structure

  11. Power Amplifier – with modified cascode str. Simplified Schematic 3-port Transformer • Cascode Structure is modified. • Tuning Para. of MN4 • Gate width • Gate bias • DC blocking Cap.

  12. Power Amplifier – with modified cascode str. Layout Characteristics • Power Stage • Class AB • 2-Differential pair • TLT for output matching • Cascode structure • Driver Stage • Class AB • 1-Differential Pair • Spiral Transformer • Cascode structure

  13. Power Amplifier – with adaptive bias circuit Simplified Schematic 3-port Transformer • Adaptive Bias Circuit is applied. • Tuning Para. • Gate width of NMOS & PMOS • Gate bias • Voltage Divider

  14. Power Amplifier – with adaptive bias circuit Layout Characteristics ABC • Power Stage • Class AB • 2-Differential pair • TLT for output matching • Cascode structure • ABC is applied. • Driver Stage • Class AB • 1-Differential Pair • Spiral Transformer • Cascode structure

  15. Power Amplifier – with adaptive bias circuit Simulation Results PAE vs. Input Power Gate Bias with ABC PAE & Gain vs. Output Power

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