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Pedram A. Riahi

Pedram A. Riahi. The MathWorks August 1 st , 2005. Outline. Background UTS-DSP Project IP Core-based SOC Testing in PLI Environment. Background. Work Experience Design Engineer, Valence Semiconductor , Dubai, UAE, 06/01-09/01

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Pedram A. Riahi

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  1. Pedram A. Riahi The MathWorks August 1st, 2005

  2. Outline • Background • UTS-DSP Project • IP Core-based SOC Testing in PLI Environment

  3. Background • Work Experience • Design Engineer, Valence Semiconductor, Dubai, UAE, 06/01-09/01 • Design Engineer, VLSI Circuits and Systems Labs, Tehran, IRAN, 09/97-09/00 • Education • PhD, Computer Engineering, Northeastern University, Boston, MA, 09/00-09/05 • MSc, Computer Engineering (Computer Architecture), University of Tehran, Tehran, IRAN, 09/96-09/99 • BSc, Computer Engineering (Software Engineering), Isfahan University, Isfahan, IRAN, 09/90-09/96

  4. BackgroundWork Experience (1) • Design Engineer, Valence Semiconductor • Design, Modeling, Implementations, and Functional Verification of an MII Interface for MAC Layer of HomePLUG IC project in Verilog using MentorGraphics ModelSim, Exemplar-Leonardo Spectrum Synthesis Tool, Xilinx Foundation Series. • Design and Modeling of an RC4 Encryption Module for MAC Layer of HomePLUG IC project in VHDL using MentorGraphics ModelSim. • Creating Design and Verification Datasheet and Specification. Currently owned by Maxim Integrated Products, Inc.

  5. BackgroundWork Experience (2) • Design Engineer, VLSI Circuits and Systems Labs • Research and Development Department of Electro-techniques Institute. • Design, Modeling, Implementation, and Functional Verification of a Pipelined Datapath for UTS-DSP joint-project, a CISC DSP Processor Based on TI DSP TMS320C54x Architecture in VHDL using MentorGraphics ModelSim, Exemplar-Leonardo Spectrum Synthesis Tool, L-Edit Layout Tool on FPGA Flex10K250. • Functional Verification of UTS-DSP joint-project in VHDL using MentorGraphics ModelSim. • Creating UTS-DSP Design and Verification Datasheet and Specification.

  6. BackgroundEducation (1) • Ph.D., Computer Engineering, Northeastern University • Thesis and Research: Developing Test Applications through Hardware Description Languages' (HDLs) C/C++ Oriented Programming Language Interfaces (PLIs), such as Verilog PLI (VPI) and VHDL PLI (VHPI), for Intellectual Property (IP) Core-based System-on-Chip (SoC) Testing using Cadence NC-Verilog and MentorGraphics ModelSim. • Courses Taken: Digital Systems Design and Interfacing with Verilog, Digital Systems Design with Hardware Description Languages (VHDL), Computer Architecture, Parallel Architectures for High-Performance Computing, Network Communications and Performance Engineering, VLSI Design, Combinatorial Optimization, Software Engineering I, Fundamentals of Computer Engineering, Mathematical Methods for EE I, Applied Probability and Stochastic Processes, Linear System Analysis. • Teaching/Research Assistantship Award. • Expert Level Teaching Assistant Accreditation Award and Outstanding Teaching Assistant Award Nomination. • HKN (Etta Kappa NU) Membership. • Advisor: Dr. Zainalabedin Navabi, Co-advisor: Dr. Fabrizio Lombardi.

  7. BackgroundEducation (2) • M.Sc., Computer Engineering (Computer Architecture), University of Tehran • Thesis: Design, Modeling, Implementation, and Verification of an Optimized Semi-RISC Instruction Set DSP Processor Based on TI DSP TMS320C54x in VHDL using MentorGraphics ModelSim, Exemplar-Leonardo Spectrum Synthesis Tool, on FPGA Flex10K250. • Ranked 28 in the M.Sc. Program Entrance Exam among 2,000. • Research Assistant in an Academic/Industry joint Project in VLSI Circuits and Systems Laboratory, Electro-techniques Institute. • Courses Taken: Design with Hardware Description Languages, Digital Systems Testing and Testable Design, Fault Tolerant Systems, Advanced Computer Architecture, Design and Synthesis of Digital Systems, Parallel Processing, Advanced VLSI Circuits, Modern Computer Networks, Design of Special Purpose Processors for Intelligent Systems, Neural Networks. • Advisor: Dr. Zainalabedin Navabi, Co-advisors: Dr. S. Mehdi Fakhraie, and Dr. Mohammadreza Movahedin

  8. BackgroundEducation (3) • B.S., Computer Engineering (Software Engineering), Isfahan University • Ranked 841 in the B.Sc. Program Entrance Exam among 2,000,000. • Thesis: Design and Implementation of Farsi Fonts for Farsi Applications. • Advisor: Dr. Mohammad Kermani

  9. UTS-DSP ProjectBlock Diagram • TI TMS320C54x • CISC Architecture • Instruction Set

  10. UTS-DSP ProjectAddressing Modes • Immediate • Absolute • Accumulator • Direct • Indirect • Memory- Mapped Registers • Stack • 32-bit Data

  11. UTS-DSP ProjectPipeline Structure • Pre-Fetch • Fetch • Decode • Access • Read • Execute

  12. UTS-DSP ProjectPre-Fetch and Fetch Stages

  13. UTS-DSP ProjectDecode and Access Stages

  14. UTS-DSP ProjectAccess Stages

  15. UTS-DSP ProjectRead and Execute Stages

  16. UTS-DSP ProjectInteractions • Memory • Peripherals

  17. UTS-DSP ProjectDesign Process • SAMSUNG’s STD80, KG60K • ALTERA’s FLEX10K • Hardware Emulator

  18. IP Core-based SOC Testing in PLI EnvironmentCore-based SOC Testing Scenario • Core-Level • Chip-Level

  19. IP Core-based SOC Testing in PLI EnvironmentGoal

  20. IP Core-based SOC Testing in PLI EnvironmentPresent Solution • Cores with Internal Parallel Scan • Wrapper Parallel Scan for Cores • Embedded Memory BIST • Other DFT Features

  21. IP Core-based SOC Testing in PLI EnvironmentPresent Solution Problems • IP Core (Black Box) • Core-Level Testing • Wrapper • Delay • Area • Chip-Level Testing • Non-optimal Test Vector Set • Tester Time

  22. IP Core-based SOC Testing in PLI EnvironmentIdeal Solution • IP Core (Compiler Intermediate Format) • Transparent via VPI while Protecting Core IP • Collapsed Chip-Level Fault List • Chip-Level Testing • Optimal Test Vector Set

  23. IP Core-based SOC Testing in PLI EnvironmentFault List / Graph Extraction in VPI • Fault Model • Stuck-at Fault • Bridging Fault • Delay Fault • Extracting Fault List • Net/Reg • Fault List Collapsing • Extracting Design Graph • Connections • Gates

  24. IP Core-based SOC Testing in PLI EnvironmentBuilding Block Components • Checking the Feasibility of Implementing Various General-Purpose Fault Simulation and Test Generation Algorithms without Necessarily Presenting a Specific Methodology. • Paving the Path for Adding other Specific-Purpose Test Applications.

  25. IP Core-based SOC Testing in PLI EnvironmentFault Simulation Algorithms • Implemented • Serial • Deductive • Critical-Path Tracing • Unimplemented • Parallel • Parallel-Pattern Single Fault Propagation • Under Implementation • Concurrent/Differential

  26. IP Core-based SOC Testing in PLI EnvironmentSerialFault Simulation • Stuck-at Fault • Fault Injection • Callback • Force • Fan-out • Fixed Automatically • Fault List • File-based I/O • Pointer-based Linked-List • Node Name • Node Handle

  27. IP Core-based SOC Testing in PLI EnvironmentGraph Extraction • Connections • Drivers • Loads • Gate Type • Output Cones • Graph List • Pointer-based • Bi-directional • Nodes: Nets/Regs • Arches: Gates

  28. IP Core-based SOC Testing in PLI EnvironmentDeductiveFault Simulation • Stuck-at Fault • Two-Value • Three-Value • Fan-out • Fault List • Pointer-based • Arches Carry out Internal Fault Lists

  29. IP Core-based SOC Testing in PLI EnvironmentCritical-Path TracingFault Simulation • Combinational Circuits • Stuck-at Fault • Fan-out • Fault List • Pointer-based • Arches Carry out both Sensitive and Critical Statuses

  30. IP Core-based SOC Testing in PLI EnvironmentTest Generation Algorithms • Implemented • Random Pattern • Pseudo Random Pattern • Under Implementation • D-Algorithm • PODEM

  31. IP Core-based SOC Testing in PLI EnvironmentFault Simulation Building Blocks • Hierarchical Fault Simulation • Flat (Structural) • Mixed-Level (Behavioral-Structural) • Required Pre- and Post-Synthesis Compiler Intermediate Formats • Level of Granularity • Threshold • Module-based • Core-based • The Higher Behavioral Level, The Better • Buffers • Fixed Automatically

  32. IP Core-based SOC Testing in PLI EnvironmentMixed-Level Fault Simulation • One-Hot • Can be Part of the Synthesis Process (Automatic)

  33. IP Core-based SOC Testing in PLI EnvironmentMixed-Level Fault Simulation

  34. IP Core-based SOC Testing in PLI EnvironmentTest Generation Building Blocks • Hierarchical Test Generation • RPTG • Color-Coded Pseudo Random • Randomly Find one or More Base Test Vector(s) Detecting Faults of a Specific Region • Level of Sensitivity • Threshold • Module-based • Core-based

  35. IP Core-based SOC Testing in PLI EnvironmentColor-Coded Pseudo Random Pattern Test Generation

  36. Thank You Questions?

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