Technology Development for InGaAs/InP-channel MOSFETs

1. MRS Spring Symposium, Tutorial: Advanced CMOS—Substrates, Devices, Reliability, and Characterization, April 13, 2009, San Francisco Technology Development for InGaAs/InP-channel MOSFETs Mark Rodwell University of California, Santa Barbara rodwell@ece.ucsb.edu 805-893-3244, 805-893-5705 fax

2. Scope of Presentation Topic of discussion is channel materials for CMOS ...the potential use of III-V materials ...and their advantages and limitations To understand this, we must examine in some detailMOSFET scaling limits

3. Zeroth-Order MOSFET Operation

4. Bipolar Transistor ~ MOSFET Below Threshold

5. Field-Effect Transistor Operation gate source drain Positive Gate Voltage → reduced energy barrier → increased drain current

6. FETs: Computing Their Characteristics

7. FET Characteristics

8. FET Subthreshold Characteristics

9. Classical Long-Channel MOSFET Theory

10. Classic Long-Channel MOSFET Theory constant-current mobility-limited Ohmic velocity-limited

11. Classic Long-Channel FET : Far Above Threshold

12. Exponential, Square-Law, Linear FET Characteristics

13. Relevance of DC Parameters Digital circuit speed largely controlled by on-state current Standby power consumption controlled by off-state current Dynamic power consumption controlled by supply Voltage → Examine VLSI Power & Delay Relationships

14. Zeroth-OrderVLSI Performance Analysis

15. CMOS Power Dissipation & Gate Delay

16. Why Large Current Density is Needed

17. Device Requirements High on-state current per unit gate width Low off-state current→ subthreshold slope Low device capacitance; but only to point where wires dominate Low supply voltage: probably 0.5 to 0.7 V

18. What Are Our Goals ? Low off-state current (10 nA/mm) for low static dissipation → good subthreshold slope → minimum Lg / Tox low gate tunneling, low band-band tunneling Low delay CFETDV/I d in gates where transistor capacitances dominate. ~1 fF/mm parasitic capacitances → low Cgs is desirable, but high Id is imperative Low delay CwireDV/Id in gates where wiring capacitances dominate. large FET footprint → long wires between gates→ need high Id / Wg ; target ~5 mA/mm @ DV= 0.7V target ~ 3 mA/mm @ DV= 0.5V

19. Improving FETs by Scaling

20. Goal double transistor bandwidth when used in any circuit → reduce 2:1 all capacitances and all transport delays→ keep constant all resistances, voltages, currents Simple FET Scaling All lengths, widths, thicknesses reduced 2:1 S/D contact resistivity reduced 4:1 If Tox cannot scale with gate length, Cparasitic / Cgs increases, gm / Wg does not increasehence Cparasitic /gm does not scale

21. FET scaling: Output Conductance & DIBL transconductance output conductance → Keep Lg / Tox constant as we scale Lg

22. FET Scaling Laws Changes required to double transistor bandwidth:

23. nm Transistors: it's all about the interfaces Metal-semiconductor interfaces (Ohmic contacts):very low resistivity Dielectric-semiconductor interfaces (Gate dielectrics):very high capacitance density Transistor & IC thermal resistivity.

24. FET Scaling Laws Changes required to double transistor bandwidth: What do we do if gate dielectric cannot be further scaled ?

25. Why Consider MOSFETs with III-V Channels ? If FETs cannot be further scaled, instead increase electron velocity: Id / Wg = qnsv Id / Qtransit = v / Lg III-V materials → lower m*→ higher velocity ( need > 1000 cm2 /V-s mobility) Candidate materials (?) InxGa1-xAs, InP, InAs ( InSb, GaAs) Difficulties: High-K dielectrics III-V growth on Si building MOSFETs low m* constrains vertical scaling, reduces drive current

26. III-V CMOS: The Benefit Is Low Mass, Not High Mobility low effective mass → high currents mobilities above ~ 1000 cm2/V-s of little benefit at 22 nm Lg

27. III-V MOSFETs for VLSI What is it ?MOSFET with an InGaAs channel Why do it ?low electron effective mass→ higher electron velocity more current, less charge at a given insulator thickness & gate lengthvery low access resistance What are the problems ?low electron effective mass→ constraints on scaling !must grow high-K on InGaAs, must grow InGaAs on Si Device characteristics must be considered in more detail

28. III-V MOSFET Characteristics

29. Low Effective Mass Impairs Vertical Scaling Shallow electron distribution needed for high gm / Gds ratio, low drain-induced barrier lowering. Energy of Lth well state For thin wells, only 1st state can be populated. For very thin wells, 1st state approaches L-valley. Only one vertical state in well. Minimum ~ 5 nm well thickness. → Hard to scale below 22 nm Lg.

30. Semiconductor (Wavefunction Depth) Capacitance

31. Density-Of-States Capacitance and n is the # of band minima Two implications: - With Ns >1013/cm2, electrons populate satellite valleys - Transconductance dominated by finite state density Fischetti et al, IEDM2007 Solomon & Laux , IEDM2001

32. Current Including Density of States, Wavefunction Depth ...but with III-V materials, we must also consider degenerate carrier concentrations.

33. Current of Degenerate & Ballistic FET

34. 2D vs. 1D Field-Effect Transistors in Ballistic Limit

35. 2D FET vs. Carbon Nanotube FET

36. Ballistic/Degenerate Drive Current vs. Gate Voltage More careful analyses by Taur & Asbeck Groups, UCSD; Fischetti Group: U-Mass: IEDM2007

37. Drive Current in the Ballistic & Degenerate Limits Error bars on Si data points correct for (Ef-Ec)>> kT approximation n = # band minimacdos,o = density of states capacitance for m*=mo & n=1

38. High Drive Current Requires Low Access Resistance

39. Materials Selection; What channel material should we use ?

41. 450 1350 AlSb 1550 200 250 500 AlAs 2170 InGaP 1900 GaSb 770 InSb 220 450 GaAs 1420 InAlAs 1460 200 InGaAs 760 InP 1350 InAs 360 150 200 170 550 200 Common III-V Semiconductors B. Brar 5.65 A lattice constant;grown on GaAs 5.87 A lattice constant;grown on InP 6.48 A lattice constant 6.48 A lattice constant

42. Semiconductor & Metal Band Alignments M. Wistey

43. Materials of Interest Source: Ioffe Institutehttp://www.ioffe.rssi.ru/SVA/NSM/Semicondrough #s only material Si Ge GaAs InP In0.53Ga0.47As InAs n 6 6 1 1 1 1 m*/m0 0.98 ml 1.6 ml 0.063 0.08 0.04 0.023 0.19 mt 0.08 mt G-(L/X) separation, eV -- -- 0.29 ~0.5 0.5 0.73 bandgap, eV 1.12 0.66 1.42 1.34 0.74 0.35 mobility, cm2/V-s 1000 2000 5000 3000 10,000 25,000 high-field velocity 1E7 1E7 1-2E7 3.5E7 3.5E7 ???

44. Drive Current in the Ballistic & Degenerate Limits Error bars on Si data points correct for (Ef-Ec)>> kT approximation n = # band minimacdos,o = density of states capacitance for m*=mo & n=1 Ge Si InGaAs InP

45. Source: Ioffe Institutehttp://www.ioffe.rssi.ru/SVA/NSM/Semicond Intervalley Separation Intervalley separation sets: -high-field velocity throughintervalley scattering -maximum electron density in channel without increased carrier effective mass

46. Choosing Channel Material: Other Considerations Ge: low bandgap GaAs: low intervalley separation InP: good intervalley separation Good contacts only via InGaAs→ band offsets moderate mass→ better vertical scaling InGaAs good intervalley separation bandgap too low ? → quantization low mass→ high well energy→ poor vertical scaling InAs: good intervalley separation bandgap too low very low mass→ high well energy→ poor vertical scaling

47. Non-Parabolic Bands

48. Non-Parabolic Bands T. Ishibashi, IEEE Transactions on Electron Devices, 48,11 , Nov. 2001,

49. MOSFET DesignAssuming In0.5Ga0.5As Channel

50. Device Design / Fabrication Goals Device gate overdrive 700 500 300 mV drive current 5 3 1.4 mA/mm Ns 6*1012 4*1012 2.5*1012 1/cm2Dielectric: EOT 0.6 nm target, ~1.5 nm short term Channel : 5 nm thickm > 1000 cm2/V-s @ 5 nm, 6*1012/cm2 S/D access resistance: 20 W-mm resistivity→ 0.5 W-mm2 contacts , ~2*1013 /cm2 , ~4*1019 /cm3 , 5 nm depth