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CASPER Workshop 2009

CASPER Workshop 2009. Cape Town, South Africa. Matt Luce. NRAO-Socorro 10/12/2009. Introduction. CASPER? CASPER Workshop 2009 Applications Hardware Tool flow Tutorials. What is CASPER?. C ollaboration for A stronomy S ignal P rocessing and E lectronics R esearch

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CASPER Workshop 2009

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  1. CASPER Workshop 2009 Cape Town, South Africa • Matt Luce • NRAO-Socorro • 10/12/2009

  2. Introduction • CASPER? • CASPER Workshop 2009 • Applications • Hardware • Tool flow • Tutorials

  3. What is CASPER? • Collaboration for Astronomy Signal Processing and Electronics Research • Original group at UC Berkeley (Dan W.) • http://casper.berkeley.edu/ • Distributed community of developers and users. • UC Berkeley, MeerKAT, NRAO, GMRT, SETI …

  4. CASPER Goals • Streamline and simplify the design flow of radio astronomy instrumentation. • Design reuse through the development of platform-independent, open-source hardware and software.

  5. CASPER Religion & Philosophy • Big projects are “dinosaurs” by release. Faster development time is an absolute necessity. • Custom backplanes are the wrong way to interface with electronics. • The signal processing libraries are a very important part of any project. • “Hardware is free.” Use commercial, off-the-shelf network hardware to connect together samplers and computing resources so that it can be easily replaced as technology improves (Moore’s Law). • The future will be clusters of general purpose computing hardware connected by fast Ethernet, instead of “hard” correlators. • There is a sweet spot of cost versus capability for deploying a new technology. Too soon and it’s very expensive. Too late and it’s outdated at deployment.

  6. CASPER Hardware: iBoB

  7. CASPER Hardware: iBoB • Virtex-II • Z-DOK • CX4 • ADC-to-iBoB-to-10GbE-to-BEE2 • http://casper.berkeley.edu/wiki/IBOB

  8. CASPER Hardware: BEE2

  9. CASPER Hardware: BEE2 • General-purpose processing module • Five Virtex-II FPGAs • 20GB DDR2 DRAM • http://bee2.eecs.berkeley.edu/

  10. CASPER Hardware: ROACH

  11. CASPER Hardware: ROACH • Reconfigurable Open Architecture Computing Hardware • Merges iBoB/BEE2 functionality onto a single board with a more modern FPGA (Virtex-5) • http://casper.berkeley.edu/wiki/ROACH

  12. CASPER Hardware: ADCs • ADC2x1000-8 (2005 - present | dual 1GSa/sec) • Dual 8-bit, 1000Msps (or single 8-bit 2000Msps), Atmel/e2v AT84AD001B • ADC1x3000-8 (2007 - present | 3GSa/sec) • Single-8 bit, 3000Msps National ADC083000 ADC • 64ADCx64-12 (2008 - present | 64x 50MSa/sec) • 64 inputs, 64 Msps, 12 bit, double wide board • ADC4x250-8 (present | quad 250MSa/sec) • Quad 8-bit, 250 Msps, Analog Devices AD9480 ADC • katADC (summer 2009 | dual 1.5GSa/sec) • Dual 8-bit, 1500Msps, National ADC08D1500 ADC • ADC2x550-12 (summer 2009 | dual 550 Msps) • Dual 12-bit, 550 Msps, TI ADS54RF63I • ADC2x400-14 (summer 2009 | dual 400 Msps) • Dual 14-bit, 400 Msps, TI ADS5474

  13. CASPER Software/Libraries • MATLAB/Simulink • Xilinx System Generator • Custom DSP Libraries • BORPH • Debian Linux • FPGA=CPU • Gateware (BOF) • File System Registers • http://casper.berkeley.edu/wiki/BORPH

  14. 2009 Workshop Overview • Applications: 3 days • Working Groups: 2 days • Hardware • Tool flow • Applications • Tutorials

  15. Application: CASPER Correlators • “The” CASPER Correlator • http://casper.berkeley.edu/wiki/CASPER_Correlator • FX using iBoB/BEE2 • PAPER (A. Parsons) • Based on CASPER • KAT-7 (J. Manley) • ROACH • Medicina • iBoB/BEE2 • 10 day development

  16. Application: CASPER Spectrometers • Fly’s Eye @ ATA (A. Siemion) • 11 iBoBs, ea. 4 independent spectrometers, 209.5 MHz w/128 channles, 0.6 ms integration time. • SERENDIP V @ Arecibo (L. Spitler) • iBoB/BEE2: 200MHz/128M channel • Nancay CoDeDi Pulsar Machine (I. Cognard) • iBoB: 400MHz/128 channel • GPU de-dispersion • GUPPI @ GBT (J. Ford) • https://safe.nrao.edu/wiki/bin/view/CICADA/NGNPPPSpecifications

  17. Application: Other • OVRO Polarimeter (M. Stevenson) • ROACH • Phased Array Processor @ SMA (R. Primiani) • iBoB/BEE2 • Modified Haystack DBE to Mark5B • Kinetic Inductance of Superconducting Resonators (L. Swenson) • ROACH driving DAC boards

  18. Hardware WG: ROACH2 • Virtex6 LX475T • 4xCX4 => 6xSFP+ • Two additional QDR • 65MB/F-engine • FTDI USB-JTAG bridge

  19. Hardware WG: future ADCs • E2v 20Gsps • ~8GHz analog bandwidth • Agilent 20 Gsps • ~13Ghz analog bandwidth

  20. Toolflow WG: Current • Pros • Ease-of-use (Graphical) • Parameterized designs • Full tool flow from DSP through bit files to drivers • Coregen • Highly efficient resource utilization • Cons • Portability • Language stability • Backwards compatibility • Simulation speed • Platform lock-in • Unit testing • Cost

  21. Toolflow WG: Future • HDL Cores • Parameterization • Simulink wrappers • Simulation • Documentation • Open source Simulink replacement

  22. Tutorials • 1: LED blinking on ROACH (Complete) • II: 10GbE (Complete) • III: Wideband Spectrometer (WIP) • IV: Pocket Correlator (WIP) • V: High Resolution Spectrometer (WIP) • Available in the CASPER SVN: • http://casper.berkeley.edu/svn/trunk/ref_designs_tutorials/workshop_2009/

  23. Questions?

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