1 / 57

AndeShape AG101 Overview

This overview provides information on the AndeShape AG101, including its AHB bus structure, various masters and slaves, and the internal and external bus connections. It also covers the features and capabilities of the N1213, MAC, LCD controller, DMA controller, and APB bridge. The device supports SRAM/SDRAM sharing, and includes interfaces for Ethernet, USB, LCD panels, memory cards, and more. It also discusses the clock control, sleep mode, wake-up events, and boot sequence.

lonc
Download Presentation

AndeShape AG101 Overview

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. AndeShape AG101 Overview www.andestech.com

  2. AG101 N1213 NCORE INCTRL Internal Bus Structure • AHB bus • Masters • N1213 • MAC • LCD controller • DMA controller • APB Bridge • Slaves • All device on AHB are slave except N1213 • APB bus • SRAM/SDRAM are sharing the IO pin on address and data • Side Band

  3. External AHB EBI for SRAM/SDRAM address and DATA SRAM, SDRAM control signals MII for Ethernet UTMI for USB LCD panel interface for STN, TFT CF, SD for memory cards I2C, SSPs/ AC97, UARTs GPIO AICE interface External interface

  4. Reset Power on reset (everything) HW reset (everything except RTC) Watch dog reset (everything except RTC and/or PMU) Sleep mode reset (everything except RTC and PMU) Clock control Normal mode Frequency Scaling mode change CPU clock FCS mode change PLL frequency Sleep mode remove power from the core, PMU monitor the wake-up event PMU

  5. Jumper set PLL clock speed Jumper set boot device bus width setup Turn on power Push button on GPIO0 Software read PMU status reg to check reset type SMR, WDT, HWR Boot sequence: power on

  6. Push reset button the sequence is similar to POR No POR No power enable No power ok Boot sequence: HW reset

  7. WDT reset condition WDT is enable Without write magic key 0x5AB9 to WdRestart reg for a period of time WDT reset will do: asserts to output pin X_reset_b, and X_hreset_b Reset everything except RTC and partial PMU Reset partial PMU depend on WDTCLR Boot sequence: WDT reset

  8. Sleep mode is triggered by software, or external signals (X_powerlow_b, GPIO) trigger interrupt to do sleep mode program Sleep mode will do SDRAMC let memory @ self-refresh mode Reset everything except PMU and RTC Assert X_reset_b, and X_hreset_b De-assert X_poweren Wake-up Wake-up on pre-program event Assert X_poweren After clocks stable, de-assert X_reset_b and X_hreset_b Sleep mode

  9. Address Map

  10. APB device Address Map

  11. N1213 PMU AHB controller APB bridge SRAM/SDRAM LCD MAC USB UART SD CF SSP/AC97 I2C RTC/Timer/Watch Dog PWM Device Overview

  12. Up to 15 AHB masters Up to 31 AHB slaves 2 level round robin arbitration Decode space 1M, 2M, 4M, 8M, ….1G, and 2G AHB controller

  13. Up to 32 APB slaves 4 DMA channels 16 sets of DMA handshake signals Decode space 1M, 2M, 4M,.., 256M APB bridge

  14. Panel I/F 24bit bus TFT panel interface Max 1024x768 75MHz Swap function for red and blue channel Input mode RGB 16(5:6:5)/24(8:8:8) Color palette 8/4/2/1 per pixel YCbCr422(16 bits per pixel) YCbCr420 OSD 12x16 font size Font variety up to 256 512 fonts/window Data format: Little/big endian, windows CE LCD

  15. SRAM/SDRAM share address and data pins SRAM 8, 16, and 32 bit ROM, flash, burst-ROM, async/sync SRAM Up to 256MB, 4 banks Little/big endian Shadow 1st and with the other banks SDRAM Max bank size 512MB, 4 banks Support 16~512 Mb devices 3 AHB channels, up to 8 AHB channels Little/big endian SRAMC/SDRAMC

  16. 10/100 Mb/sec MII Ethernet PHY Half/Full duplex DMA engines for TX/RX Programmable AHB burst size Wake up on Link status change, Magic packet, Wake up frame Little endian MAC

  17. USB 2.0 16 bit UTMI Automatic CRC5 CRC16 gen/chk Support suspend mode, host resume and device remote wake-up Easy endpoint configuration USB device

  18. NS 16C550A compatible Up to 11520 Kbps 5,6,7, and 8 bit data 1, 1.5, 2 stop bit Even, odd and not parity check Support handshake mode DMA UART

  19. SD SD v1.0 SD/MMC bus protocol Handshake DMA mode for large data transfer Built-in 7/16-bit CRC generation and checker Variable clock rate: 0~25 MHz Hot insertion/removal Write protect for SD card SD

  20. Common, attribute memory, and IO access DMA and PIO mode Programmable 8/16 –bit mode Support power and reset control function CF

  21. SSP, SPI, microwire, IIS, and AC-link protocol 4-32 bit serial data Internal or external serial bit clock Programmable LSB/MSB first Handshake DMA SSP/AC97

  22. Support standard and fast mode Glitch suppression 7-bit, 10-bit and general call address modes Programmable slave address Support master-tx, master-rx, salve-tx, slave-rx Support multi-master mode I2C

  23. Clock source could be PCLK or 32.768 Osc. RTC: per-sec, per-minute, per-hour, and per-day int Timer: 3 independent 32-bit counter, each timer has 2 match registers WD 32-bit down counter RTC/Timer/Watch Dog

  24. 2 pulse width modulation channels 6-bit clock divider 10-bit period control 10-bit duty cycle register PWM

  25. Leopard Guidelines www.andestech.com

  26. A-ICE Connector LCM Connector EBI/X-BUS LED Nor Flash GPIO Push Buttons SD/MMC Oscillator SDRAM VIRTEX AHB Connector MII Connector Reset Button Flash Power On Button DC-IN Jack RJ45 Power Switch UARTs Audio Phone Jack ADP-XC5FF676 Main Board Overview

  27. ADP-XC5 System Block Diagram

  28. Xilinx XC5VLX110-1FF676 FPGA 144-pin SO-DIMM for SDRAM 32MB on-board NOR flash 10/100 Ethernet PHY 2 DB9 UART ports X-Bus expansion AHB bus connector SD card slot IDE connector LCD I/F AC97 Audio Codec On Board Device

  29. ADP-XC5FF676 Devices • Devices on APB • AHB-APB bridge • PMU • I2C • GPIO • Interrupt controller • Watch dog timer • Timer • RTC • UART • SSP • I2S/AC97 • SD/MMC • Devices on AHB • SDRAM controller (128MB) • LCD controller • DMA controller • MAC controller • USB 2.0 device controller • SRAM controller (512KB) • Flash controller (32MB) • AHB Bus controller

  30. Platform IP Ready in ADP-XC5 N903 Bus Controller MAC 10/100 USB2.0 AHB Bus LCD Controller SDRAM Controller DMA Controller SRAM Controller AHB to APB Bridge PWM I2C GPIO INTC WDT Timer RTC APB Bus Power Manager IrDA ST UART BT UART FF UART SSP CF I2S SD/ MMC

  31. CPU frequency is 80 MHz : N1213; 40MHz : N903 AHB Clock is 40 MHz XILINX Virtex5 LX110 64MB SDRAM SO-DIMM 32MB NOR Flash X-Bus for AIT Chip 10/100 Ethernet SD card slot 2-Digit debug port AndesICE port 5 push bottons 2 UART ports ADP-XC5FF676 Profile

  32. Prolific USB-to-Serial Software (If you need) PL-2303 Driver PL-2303.Driver.Installer.exe Terminal Software TeraTerm teraterm_utf8_452.exe TFTP Server for Windows Tftp32 tftpd32.284 Software Installation

  33. Prolific USB-to-Serial Setting 控制台/系統/硬體/裝置管理員/連接埠 (COM 和 LPT) TeraTerm Setting Start ‘TeraTerm’ and select ‘Setup / Serial port…‘ from the menu Port: COM3 Baud Rate: 38400 Data: 8bit Parity: none Stop: 1 bit Flow control: none Software Setting

  34. TeraTerm Software Setting

  35. Hyper Terminal Software Setting

  36. Tftp32 Software Setting

  37. Leopard and Laptop are connecting via Switch 控制台 / 網路連線 / 區域連線 / 內容 Networking Setting

  38. AndeShape eBIOS booting

  39. Plug in DC power to main board Turn power switch to ‘ON’ Press push-button “SW4” Boot procedures

  40. ------------------------------------------------------------------------------------------------------------------------------------------------------------ Andes Development Platform Diagnosis Menu, Built@Aug 25 2008 (release: 1.1) CPU: N10 Platform: EVB-AG101 Cache: no cache CPU: 40MHz HCLK: 40MHz ------------------------------------------------------------------------------ ( 1) SDRAM Test ( 2) Timer Test ( 3) DMA Test ( 5) UART Loopback Test ( 6) UART DMA Test ( 9) Watchdog Test (10) Watchdog Reset Test(11) MAC Loopback Test (12) Flash Test (13) SODIMM Sizing (14) SDRAM(bnk1,2) (17) AC97 Test (18) AC97 DMA Test (21) LCD Test (23) Query RTC (24) RTC Alarm Test (25) GPIO Test (55) CLI (67) Set Console's UART (75) Burnin Test (93) Exec Img on LM(I/D) (94) Dhrystone Test (95) Boot Selection (97) CopyImageFromCard (99) Setup Command>> Diagnostic Main Menu

  41. Basic Register Read Write via CLI command Run a C program to show numeric to 7SEG LED Demo

  42. To write a C program to show odd/even numeric on 7SEG LED Write a C program Do compilation Upload load image file by SD card CLI command Lab1 – 30 minutes

  43. HW Development Solution www.andestech.com

  44. . SW development . AICE debug Download your FPGA design SOC platform with N903 User Define Module AHB Extension Bus ADP-XC5 Development Board ADP-XC5Development Board AHB Extension Bus – Two Leopards Solution

  45. N903 DMA MAC AHB Extension Header User Define Circuit AHB Bus DRAM LCD Uart / SPI AHB Extension Bus – Quick SOC Integration

  46. AHB Basic Protocol

  47. AHB Extension Bus Header

  48. Address Phase Master issue command haddr hwrite htrans hsize hburst Data Phase Master/Slave read and write data hdata Slave response Hready hresp Bidirectional Bus Control

  49. Ext. AHB Master Master No. 5 X_hm5_hbusreq X_hm5_hgrant Master No. 6 X_hm6_hbusreq X_hm6_hgrant Reserved External Devices

  50. Ext. AHB Slave Slave No. 13,15,17,18,19,21,22 X_hs13_hsel, X_hs15_hsel, X_hs17_hsel, X_hs18_hsel, X_hs19_hsel, X_hs21_hsel, X_hs22_hsel Memory Size : 1MB, 1MB, 1MB, 1MB, 1MB, 256MB, 128MB, Address Map : 0x90A0_0000, 0x90C0_0000, 0x90E0_0000, 0x90F0_0000, 0x9200_0000, 0xA000_0000, 0xB000_0000 Reserved External Device

More Related