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Instructions and Addressing

Instructions and Addressing. http://www.pds.ewi.tudelft.nl/~iosup/Courses/2011_ti1400_4.ppt. Lecture 1 Making functions. nand gates. A. Y. ADD. B. Y. A,B. . time. 2. Lecture 1 Making functions. Circuit Diagram http://xkcd.com/730/. Lecture 2 Programmable device. Programmable

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Instructions and Addressing

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  1. Instructions and Addressing http://www.pds.ewi.tudelft.nl/~iosup/Courses/2011_ti1400_4.ppt

  2. Lecture 1Making functions nandgates A Y ADD B Y A,B  time 2

  3. Lecture 1Making functions Circuit Diagram http://xkcd.com/730/

  4. Lecture 2Programmable device Programmable Device 3 2,1 • READ(X) means read next input value from input stream and store it internally as variable X • WRITE(X) means put value in variable X on output stream • ADD(X,Y,Z) means assign value of X+Y to Z input stream output stream program READ(X) READ(Y) ADD(X,Y,Z) WRITE(Z)

  5. X: 1 Y: 2 Z: 3 • • READ(X) READ(Y) ADD(X,Y,Z) WRITE(Z) Lecture 3Von Neumann Architecture Memory Central Processing Unit TEMP_A: TEMP_B: RESULT: arithmetic unit Input IR: CONTROL Output PC:

  6. Problem: How to Represent and Use Data? • Representation • Arithmetic • Conversion

  7. X: 1 Y: 2 Z: 3 • • READ(X) READ(Y) ADD(X,Y,Z) WRITE(Z) Lecture 2Von Neumann Architecture Memory Central Processing Unit TEMP_A: TEMP_B: RESULT: arithmetic unit Input IR: CONTROL Output PC:

  8. Problem: How to Represent and Use Data Instructions? • Representation • Use (Addressing Data)

  9. Instructions and Addressing Memory Layout Types of Instructions Use of Accumulator/Registers Execution of Instructions Addressing 9

  10. X: 1 Y: 2 Z: 3 • • READ(X) READ(Y) ADD(X,Y,Z) WRITE(Z) Computer System Main Memory Central Processing Unit registers arithmetic unit Input IR: control unit Output PC: Data and Instructions Program Counter Instruction Register

  11. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Main Memory Addressing Address0 Address31 8 16 24 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 0 0 0 0 0 0 0 0 0 Byte(8 bits) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Word(16-64 bits)

  12. Q1: How many bits required to address? • 1GB of memory • By Bit • By Byte • By Word of 32 bits • 1TB of memory • By Bit • By Byte • By Word of 32 bits • 1KB of memory • By Bit (13) • By Byte (10) • By Word of 32 bits (8) • 1MB of memory • By Bit (23) • By Byte (20) • By Word of 32 bits (18) Q2: How much memory can be addressed by byte for a 32-bit architecture? Q3: Why use byte memory addressing?

  13. instruction instruction instruction instruction instruction instruction Instruction and wordlength (1/3) word word address address 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 instruction instruction instruction instruction

  14. instruction instruction instruction instruction instruction instruction instruction instruction instruction instruction instruction instruction Instruction and wordlength (2) word address 0 1 2 3 4 5 6 7 8 9 10

  15. instruction instr. instr instruction instr. instr instruction instr. instr instruction instr. instr instruction instr. instr instruction instr. instr Instruction and wordlength (3) word address 0 1 2 3 4 5 6 7 8 9 10

  16. 32 bit word formats 32 bit 31 30 1 0 a two’s complement number byte byte byte byte 4 ASCII characters opcode specifier operand specifiers a machine instruction

  17. 0 0 1 2 3 0 1 1 4 5 6 7 2 2 8 9 - - - - - - - - - - Byte ordering (endianness) Little endian e.g., Intel Big endian e.g., Motorola PowerPC 68k Word Index 3 2 1 0 7 6 5 4 - - 9 8 - - - - - - - - Jonathan Swift’s Gulliver’s Travells

  18. Q1 (the NUXI problem) • What problems can occur in porting data between machines with big-endian and little-endian storage? (Hint: networked machines) Q2 Why use the little endian byte ordering? • (Hint: value 4 as single- and multi-byte) Q3 Why use the big endian byte ordering?

  19. Instructions and Addressing Memory Layout Types of Instructions Use of Accumulator/Registers Execution of Instructions Addressing 2.1. Data Copy Operations 2.2. Arithmetic And Logic Ops. 2.3. Program flow control Ops. 2.4. I/O operations 19

  20. Types of Instructions • There are 4types of instructions • Data Copy operations • between memory and registers • between memory locations • between registers • Arithmetic and Logic operations • Program flow control operations • I/O operations

  21. Symbolic notation • Copy instructions [R1]M(LOC) • Arithmetic operations M(C)M(A) + M(B) • LOC, A, and B are memory addresses • M(address)means contents of memory location at address. • [R]means contents of register R.

  22. Operand specification formats • Three-address instructions format: INSTR source#1,source#2,destination example: Add A,B,C means: M(C)M(B) + M(A) • Problem: 3-address instructions means long instruction words. • If k bits are needed for memory addressing, then 3k bits are needed for addressing operands. (k=32 for 32-bit platforms.)

  23. Operand specification formats • Two address instructions format: INSTR source, destination example: Add A,B means: M(B)M(B) + M(A) • Problem: 2-address instructions mean somewhat long word or multiple FETCHes per instruction. • If k bits are needed for memory addressing, then 2k bits for addressing operands. (k=32 for 32-bit platforms.)

  24. Two address instruction Additional Problem: Operand Override Add A,B • Two operand instructions destroy contents of the B location • Need other instruction to avoid that: Move B,C • We then have Move B,C Add A,C meaning: M(C)M(B); M(C)M(C) + M(A);

  25. One address instructions • One address • have implicit source (often called Accumulator) Load A Add B Store C meaning [Accu ]M(A); [Accu ][Accu ] + M(B); M(C)[Accu ]

  26. Instructions and Addressing Memory Layout Types of Instructions Use of Accumulator/Registers Execution of Instructions Addressing 26

  27. Registers • Many computers have a number of General-Purpose registers inside the CPU • Access to registers is faster than to memory locations • Used to storetemporarydata during processing • Registers require less bits of addressthan main memory

  28. Register addressing • Let Ridenote register • General operation ADD A,B,Ccan be broken down to Move A,R0 Add B,R0 Store R0,C meaning [R0]M(A); [R0][R0] + M(B); M(C)[R0]

  29. opcode operand Instruction Formats (Summary) general format opcode specifier operand specifiers one operand addressing two operand addressing opcode operand operand

  30. Accumulator architecture CPU Accumulator PC Main Memory

  31. Question How many instructions can be defined when the opcode field is 5bit ?

  32. Example 4 bits 12 bits m instruction operand opcode 0 15 accu sign bit

  33. Instruction set

  34. Multiple register architecture CPU R0 R2 R1 R3 Main Memory

  35. Instructions and Addressing Memory Layout Types of Instructions Use of Accumulator/Registers Execution of Instructions Addressing 35

  36. Move A,R0 Add B,R0 Move R0,C • • …... …... ……. Straight-line sequencing address i i+4 i+8 A B C Program for M(C)=M(B)+M(A)

  37. Move N1,R0 Add N2,R0 Add N3,R0 • • Add Nn,R0 Move R0,S Straight-line sequencing address i i+4 i+8 i+4n-4 i+4n Program for addition of n numbers

  38. Branching Clear R0 Move N,R1 Decr R1 Branch>0 L Move R0,S Determine address of “next” number and add it to R0 L S N N1 Nn program loop ...... n Program for addition of n numbers

  39. Common branch conditions • N (negative) set to 1of result is negative • Z(zero) set to 1 of result is zero • V(overflow) set to 1 of result overflows • C (carry) set to 1 of carry-out results

  40. Question Why is the carry condition important?

  41. Instructions and Addressing Memory Layout Types of Instructions Use of Accumulator/Registers Execution of Instructions Addressing 5.1. Addressing Modes 5.2. Immediate Addressing 5.3. Direct Addressing 5.4. Indirect Addressing 5.5. Index Addressing 41

  42. Addressing modes • Addressing modes determine how the address of operands is determined • Typical 4addressing modes • immediate addressing • direct addressing • indirect addressing • index addressing

  43. instruction opcode specifier operand ADD # -1 JNZ 10 • • 10 example: simple counting loop Immediate addressing (1)

  44. Immediate addressing (2) • Advantages: • no additional calculations needed to obtain operand • fast • Disadvantages: • Operand value must be known • Operand value cannot be changed • Limited no of bits available • Notation:MOVE #200,R0 • Meaning:[R0]  200

  45. instruction opcode specifier mem or reg address ADD 13 JNZ 10 • # -1 10 memory or registers 13 Direct addressing(1)

  46. Direct addressing(2) • Advantages: • Operand separate from instruction • Can be changed • Full word length available • Disadvantages: • More memory accesses • More storage occupation • Notation:ADD R1,R2 • Meaning:[R2]  [R2] +[R1] • Also called “Absolute addressing” (Ham.)

  47. instruction opcode specifier mem or reg address op. address operand ADD (12) JNZ 10 13 # -1 10 memory or registers 13 Indirect addressing (1)

  48. Indirect addressing (2) • Advantages: • Actual address of operand is not in instruction • Can be changed • Disadvantages: • Even more memory or register references • More memory occupation • Notation:ADD (R1),R2 • Meaning:[R2]  [R2] + M([R1])

  49. Example indirect addressing Clear R0 Move N,R1 Move #N1,R2 program loop Add (R2),R0 L Add #4,R2 Decr R1 Branch>0 L Move R0,S S N n N1

  50. + Index addressing (1) instruction opcode Reg index operand operand registers memory or registers

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