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Beam Secondary Shower Acquisition System: Igloo2 SERDES Manual Initialization. Student Meeting Jose Luis Sirvent PhD. Student 31 /03/2014. Igloo2 GBT-FPGA (STD) implementation status Substitute Xilinx IP’s by Microsemi IP’s (Others.. not). Transceiver with EPCS @ 4.8GBPS:
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Beam Secondary Shower Acquisition System:Igloo2 SERDES Manual Initialization Student Meeting Jose Luis Sirvent PhD. Student 31/03/2014
Igloo2 GBT-FPGA (STD) implementation statusSubstitute Xilinx IP’s by Microsemi IP’s (Others.. not) • Transceiver with EPCS @ 4.8GBPS: • - A lot of configuration registers • - Big amount of documentation • - Different implemented protocols (not needed) • - Power-Up Initialization needed (HPMS) • - Synchronization issues • - Needed standalone testing and verification
Igloo2 SERDES Testing (EPCS-4.8Gbps) Looping the lines, TX & RX simulation and start-up sequence
Igloo2 SERDES Testing (TX & RX @ EPCS 4.8GBPS)Working with the Dev. Board and the means it provides Parallel Received Data (20 bits): “11110 00011 11111 1XXXX” Parallel Input Data (20 bits): “111100001111 1111 XXXX” FramePos 3 2 1 0
Igloo2 SERDES Testing (TX & RX @ EPCS 4.8GBPS)Working with the Dev. Board and the means it provides Parallel Received Data (20 bits): “11110 00011 11111 1XXXX” Parallel Input Data (20 bits): “111100001111 1111 XXXX” SERDES Rx Tx FramePos 3 2 1 0 DataRx_0 DataRx_1 … DataRx_19 DataTx_0 DataTx_1 … DataTx_19
GBT-FPGA Overview in Igloo2(Clock Management) GBT_BANK (Very simplified view) SERDES_INIT_MASTER APB_BUS (PLL) Data_In (83 bits) @40Mhz Tx_Word (19 bits) @ 240MHz Tx_CLK (240MHz) GBT_TX Scrambler Encoder Gearbox GBT_MGT SERDES_0 Vendor Specific IP TX_Data_P (4.8Gbps) TX_Data_N (4.8Gbps) TX_Word_CLK (240MHz) TX_Frame_CLK (40MHz) RefCLK1_P (120MHz) RefCLK1_N (120MHz) Rx_CLK (240MHz) RX_Data_P (4.8Gbps) RX_Data_N (4.8Gbps) Rx_Word (19 bits) @ 240 MHz Data_Out (83 bits) @ 40Mhz GBT_RX Gearbox Decoder Descrambler RX_Word_CLK (240MHz) RX_Frame_CLK (40MHz) RX_PLL TX_PLL
GBT-FPGA Overview in Igloo2(Clock Management) Dev. Kit FPGA GBT_BANK (Very simplified view) SERDES_INIT_MASTER APB_BUS (PLL) Data_In (83 bits) @40Mhz Tx_Word (19 bits) @ 240MHz Tx_CLK (240MHz) GBT_TX Scrambler Encoder Gearbox GBT_MGT SERDES_0 Vendor Specific IP TX_Data_P (4.8Gbps) TX_Data_N (4.8Gbps) TX_Word_CLK (240MHz) !! TX_Frame_CLK (40MHz) RefCLK1_P (120MHz) RefCLK1_N (120MHz) Rx_CLK (240MHz) RX_Data_P (4.8Gbps) RX_Data_N (4.8Gbps) Rx_Word (19 bits) @ 240 MHz Data_Out (83 bits) @ 40Mhz GBT_RX Gearbox Decoder Descrambler RX_Word_CLK (240MHz) RX_Frame_CLK (40MHz) RX_PLL TX_PLL
SERDES_INIT_MASTER: • High Performance Memory Subsystem (HPMS): • The responsible for PeriphericsInit Quick, simple and transparent to user. • Problem We need 2 Pll available per GBT_Bank and MG2010 has only 2!! • Possible Solution Test with 2 Dev Board, one as TX and other as RX (Not possible to simulate our assembly, only some parts) • Resources: • 1 x PLL , 1 x Fab_Osc , 1 x CoreConfigMaster (IP), 1 x CoreConfigP (IP), 1 x CoreResetP (IP) ,1 x CoreAHBLite (IP) • Manual APB Master & ROM for SERDES Configuration: • Very few resources needed: 1x Fab_Osc, 1 x ROM • Better control over what’s happening on the SERDES block • No need of System Builder (visual interface) which sometimes crashes! • Need to understand Serdes Registers Initialization protocol and replicate it manually • In only one FPGA Dev. Kit we can test all the system Tx & RX with USB. Picture from M. Barros Marin
Manual APB Master & ROMFor SERDES Configuration and Initialization: • SERDES_INIT_REGISTERS.vhdl: • Package that implements 2 ROM • 1 x Data_Rom Registers values • 1 x Addess_Rom Registers Addres • Up to 73 registers to initialize • Values assignments one by one based on Wizard • Needed to understand some internal tricks and changes done by HPMS • SERDES_APB_MASTER.vhdl: • Implementation of APB bus protocol 32 bits • Replicates the values and time structure done by HPMS in every line respecting APB protocol. • Runs the complete initialization of all registers in ROM • We only need here the Fab_OSC at 50Mhz
Manual APB Master & ROMFor SERDES Configuration and Initialization: It works!! (Post-synthesis sim) Tx & RX @ 4.8Gbps Now we have the Two M2G010 PLL’s available for GBT-Bank !!
Off-Topic comments: • 1. Meeting with E.Picatoste & D.Gascon: • Designers ICECAL ASIC for LHCb. • Considered an interesting Plan-B for QIE10. • 4 ch ASIC seems to reach our specs in terms of timing (25ns and DC), for Dyn.Range we need to work with 2-3 in parallel (Dyn = 4e4 4fC – 15pC). We’ll need external ADC’s (Rec. AD41240 40Krad) • Working principle is the same as the one we use in the surface, also from LHCb VFC. • They will provide soon some samples for testing (pCVD splitting chain and noise) Current system on Surface
Off-Topic comments: • 1. Meeting with E.Picatoste & D.Gascon: • Designers ICECAL ASIC for LHCb. • Considered an interesting Plan-B for QIE10. • 4 ch ASIC seems to reach our specs in terms of timing (25ns and DC), for Dyn.Range we need to work with 2-3 in parallel (Dyn = 4e4 4fC – 15pC). We’ll need external ADC’s (Rec. AD41240 40Krad) • Working principle is the same as the one we use in the surface, also from LHCb VFC. • They will provide soon some samples for testing (pCVD splitting chain and noise) Current system on Surface
Off-Topic comments: • 2. Possibility for final prototype (good to keep in mind): • Workshop on FPGAs on high Energy physics: https://indico.cern.ch/event/300532/timetable/#20140321 • Other developments could be interesting for us: CMS ngCCM board with Igloo2 Tom O ‘ Baron. FPGA For High Energy Physics Workshop—LHCb Inputs. Univ. of Maryland 21/03/2014
