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6-Bit Serial Multiplier

6-Bit Serial Multiplier. Thu Nguyen Kenny Yip Chao-Ton Yang Ming Li Advisor: Prof. David Parent Dec 6, 2004. Introduction. We design a 6-bit serial.

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6-Bit Serial Multiplier

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  1. 6-Bit Serial Multiplier Thu Nguyen Kenny Yip Chao-Ton Yang Ming Li Advisor: Prof. David Parent Dec 6, 2004

  2. Introduction • We design a 6-bit serial. • The advantage of this design over the parallel circuit is the reducing of required hardware and input, output routing when the high clock rate is not important factor in application.

  3. Specifications • Clock f = 100 MHz, duty cycle = 50% • Output Cload = 10 pF • Power < 500 mW • Tpavg < 5ns • Area < 600 mil2

  4. Block Diagram

  5. 1-bit schematic

  6. Schematic

  7. Longest Path Calculations

  8. D Flip-Flop schematic

  9. D Flip-Flop transient response

  10. Full Adder schematic

  11. Full adder verilog waveform

  12. Full Adder transient response

  13. Verilog Waveform

  14. 6bit serial multiplier simulation Tpavg = 4.2 ns

  15. Power Consumption • Pavg=1/2 x CL x f x VDD2 • P avg = 1/2 x 10 x 10-12 F x 100 x 106 Hz x 52 = 12.5mW for 1 component. • Power transient response of entire circuitry read from the simulation P = 148mW.

  16. DRC & Extraction

  17. LVS

  18. Complete Design Layout

  19. Test results • Tpavg = 4.2ns (< 5ns) • Total area A = 345 x 310mm(1070 mil2 > 600 mil2) • Power P = 148mW (< 500 mW)

  20. Summary • Product test results meet most of specifications except the layout area are larger than 600 mil2 target specifications but we could easily reduced it if we have more time to rearrange all the compoments and routing. So Layout area is not actually a problem. • This a very challenge project, although we were not having much time left for project after the other heavy class works, this is the best we can accomplish.

  21. Acknowledgements • Thanks to Cadence Design Systems for the VLSI lab • Thanks to Professor D. Parent • Thanks to our EE166 classmates

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