Portable FPGA Designs with Interface Adaptive Module

1. Portable FPGA Designs with Interface Adaptive Module Haiqian Yu , Dr. Miriam Leeser hyu@ece.neu.edumel@ece.neu.edu Abstract Reconfigurable Computing Board Adaptive Module VHDL provides designers a way to describe the system not tied to a specific methodology or target technology. However, for designs with off-chip memory or I/O access, interface to the memories or I/O ports varies with different implementations. For maximal reuse of original VHDL code while changing FPGA target board, we introduce an adaptive module put between memory interface and core design to isolate these two parts. By this means, only the adaptive module need to be modified. An typical example, parallel-beam backprojection is used to illustrate how we can easily port our VHDL code to different boards with little modification only to the adaptive module. • The basic idea of adaptive module is to isolate the computing and memory access, with name Core Design and Memory Interface respectively. • Memory interface may use very different handshaking signals for different target hardware. • Change target hardware is very common so that re-use of original VHDL code is very important. • Adaptive module is proposed for maximum re-use of VHDL code. WildStar and FireBird are two commercial FPGA computing board from Annapolis Micro Systems, Inc. They are our target hardware implementation of parallel-beam backprojection. They have different FPGA chip, different board structure and different user-supplied interface code. • Some pseudo-code are provided in VHDL format • Actual processes are much more complicated • Address Update Process (AUP) and Control Signal Update Process (CSUP) belong to the adaptive module. • Data Computing Process (DCP) is part of core design. • Commented line can be uncomment when necessary Parallel-beam Backprojection • Parallel-beam backprojection is widely used in Computed Tomography to reconstruct the slice of the object. • It is an memory intensive and computation intensive algorithm and hardware speedup is necessary for real-time processing • FPGA implementation is used for flexibility and high speed. WildStar Schematic Diagram and the board FireBird Schematic Diagram and the board AUP: Process (clk, reset) Begin if(reset = '1') then address <= some initial value; elsif(rising_edge(clk)) then ------------------------------------------- -- If memory interface provides ack signal -- if(ack = '1') then -- address <= next address; -- end if; -- end if; ------------------------------------------- address <= next address; -- No ack signal end if; End process CSUP: Process(clk,reset) Begin if(reset = '1') then no read/write request; elsif(rising_edge(clk)) then check and make sure there is no data conflict. ------------------------------------------- -- If memory interface provides ack signal -- if(ack = '1') then -- send next read/write request; -- end if; ------------------------------------------- send next read/write request; -- No ack signal end if; End process *************************************************************** DCP: Process(clk, data_valid) Begin if(rising_edge(clk)) then if(data_valid = '1') then process the data; else stall the pipeline and wait for the data_valid signal; end if; End process; Reprojection Data Acquisition Hardware Consideration and Data Flow Backprojection Our implementation use fixed point. The bit-width are select according to the software simulation result to ensure the minimum area while the visual quality of the images are not compromised. Sinogram data Reconstructed image Performance • Adaptive module won’t affect the processing time. • For our 16-way parallel design, 74.72% of the code are core code and can be re-used for different platform. Future Work • More general adaptive module for different number of input/output memories. • More advanced FPGA chips can be used for better performance