EE434 ASIC & Digital Systems

1. EE434ASIC & Digital Systems Jacob Murray School of EECS Washington State University jmurray@eecs.wsu.edu

2. Course ProjectPart 1

3. System on chip Technology Scaling Transistor count: exponential growth Prohibitive manufacturing costs 10M$ - 100M$ 0.13micron designs Over 100 millions for today’s SoCs + Reusability Platform Based Design Emergence of Multi-Processor SoC Platforms

4. Evolution of design methodologies Source:Henry Chang et al “Surviving the SoC Revolution: A Guide to Platform-Based Design” • Semiconductor Intellectual Property (SIP) • Functional SIP • Memory, processors, DSPs, I/O, UARTs …….

5. Network on chip • Modification of inter-block communication • IPs communicate via network-oriented protocols • Structured interconnect template • Independent optimization of the communication fabric • Intelligent switches (I2Ps) establish the communication

6. Proposed Architectures

7. Example Layout

8. Data transmission • Packet-based communication • Low memory requirement • Wormhole routing • Deterministic • LCA, e-cube • Virtual channels • enhance channel utilization

9. Throughput characteristics • 4 virtual channels is a reasonable trade-off

10. Switch architecture

11. Switch architecture Design This

12. Arbitration • Different types of arbiters • Matrix, round-robin, queuing • Matrix arbiters are faster • The arbiter circuit essentially consists of a priority matrix, which stores the priorities pij of the requesters and grants generation circuits used to grant (gnti) resources to requesters. • The priority matrix stores priorities between n requesters in a binary n-by-n matrix. • Each matrix element [i, j] records the binary priority between each pair of inputs. • For example, suppose requester i has a higher priority than requester j, then the matrix element [i, j] will be set to 1, while the corresponding matrix element [j, i] will be 0 • A requester will be granted the resource if no other higher priority requester is bidding for the same resource. Once a requester succeeds in being granted a resource, its priority is updated and set to be the lowest among all requesters.

13. Flit-level arbitration Example: • Requestor 2 is granted access • Row 2 is set to 0, column 2 is set to 1 • requester 2 has the lowest priority now

14. Design Details • Design Hierarchy Arbiter Priority Matrix Grant

15. Design Details Priority Matrix SR Latch Update

16. Arbitration mechanism

17. Entity of the Priority Matrix entity p_matrix is port ( clk, reset : in std_logic; grant1, grant2, grant3, grant4 : in std_logic; p12, p12b, p13, p13b, p14, p14b : out std_logic; p23, p23b, p24, p24b, p34, p34b : out std_logic); end p_matrix;

18. Architecture of the Priority Matrix component update port ( clk : in std_logic; reset, grant_col, grant_row : in std_logic; p, pb : out std_logic); end component; u12 : updateport map ( clk => clk, reset => reset, grant_row => grant1, grant_col => grant2, p => p12, pb => p12b); Six these types of port mapping may be needed

19. Update Block entity update is port ( clk : in std_logic; reset, grant_row, grant_col : in std_logic; p, pb : out std_logic); end update;

20. Grant Block entity grant is port ( clk : in std_logic; r1, r2, r3, r4, reset : in std_logic; p12, p12b, p13, p13b, p14, p14b : in std_logic; p23, p23b, p24, p24b, p34, p34b : in std_logic; grant1, grant2, grant3, grant4 : out std_logic); end grant;

21. Arbiter Block (The Top Level Module) entity arbiter is port ( clk : in std_logic; r1, r2, r3, r4 : in std_logic; grant_1, grant_2, grant_3, grant_4 : out std_logic; reset : in std_logic); end arbiter; r1, r2, r3 and r4 are the requests coming from external sources

22. Structure of the Top Level Block component grant port ( clk : in std_logic; r1, r2, r3, r4, reset : in std_logic; p12, p12b, p13, p13b, p14, p14b : in std_logic; p23, p23b, p24, p24b, p34, p34b : in std_logic; grant1, grant2, grant3, grant4 : out std_logic); end component;

23. Structure of the Top Level Block component p_matrix port ( clk : in std_logic; reset, grant1, grant2, grant3, grant4 : in std_logic; p12, p12b, p13, p13b, p14, p14b : out std_logic; p23, p23b, p24, p24b, p34, p34b : out std_logic); end component;

24. Interfacing of the Arbiter with FIFO Buffers • At the input side of the switch blocks the request signals to the arbiter comes from the FIFO buffers • When the FIFO buffers are full they send a full signal to the arbiter • These full signals are the request signals to the arbiter • The arbiter needs to arbitrate among the FIFO buffers