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Results of a Sliced System Test for the ATLAS End-cap Muon LVL1 Trigger

Results of a Sliced System Test for the ATLAS End-cap Muon LVL1 Trigger. H.Kano (University of Tokyo) 1. System overview 2. Components (PS, HpT, RO, CTRL, S/W) 3. SLT experimental setup 3. Test results 4. Conclusion. Introduction.

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Results of a Sliced System Test for the ATLAS End-cap Muon LVL1 Trigger

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  1. Results of a Sliced System Test for the ATLAS End-cap Muon LVL1 Trigger H.Kano (University of Tokyo) 1. System overview 2. Components (PS, HpT, RO, CTRL, S/W) 3. SLT experimental setup 3. Test results 4. Conclusion

  2. Introduction • For the muon endcap LVL1 trigger system, full spec. custom ASICs and modules have been developed and tested. • We have completed to build these ASICs and modules. • Integration test of full components for the sliced system has been done.

  3. Block Diagram Trigger Part MUCTPI PP G-LINK (20m) PPG50 HPT SL PS Pulse pattern generator LVDS (7m) triplet ROD doublet doublet SSW ROB ROD 3700 TGCs 320k channels Readout Part

  4. 125ns (required) 96ns PS Board & ASIC From ASD 256ch input LVDS-IN PP-ASIC PS-ASIC LVDS-OUT To H-pT

  5. PP ASIC: 0.6mm 0.35mm 50,000gates analog + digital LVDSrx, fine-delay, and BCID function PS Board & ASIC PS ASIC: 0.35mm 250,000gates readout and L-pT trigger function

  6. High-pT Board G-Link OUT To SL From PS LVDS IN High-pT ASIC 0.35mm BGA256 75ns (Required : TDR) 33ns

  7. LVDS module Glink module Readout System FIFO TO CTP From SSW CPU SDRAM full func. ROD FPGA module SSW From PS TO ROD Readout System

  8. JTAG CORE BUILDER HSC CCI Control System JTAG Using JTAG core logic generating script These JTAG cores work fine. HSC-CCI (remote VME/JTAG control system) VME1 VME2 optical cable

  9. Run Control Conf. DB editor PP Control Software Integrated Control Software based on the ATLAS online framework i Please visit our poster

  10. Pulse Gen. ROD SSW PS SLT Control HpT Experimental Setup SSW ROD Pulse Gen. PS HpT SL CCI bit pattern JTAG HSC SLT CTRL SL

  11. Result of the forward wire Result (Trigger Part) Check Trigger System Hardware Test bit-pattern compare Trigger System Simulation

  12. System Latency 1176ns < 1250ns(TDR) acceptable

  13. Software Result (Control Part) System Configuration Run Control HSC-CCI (remote VME control system) HSC HpT Configuration by JTAG via HSC-CCI HpT Control by VME via HSC-CCI Remote VME/JTAG control : acceptable HpT CCI JTAG JTAG Operation : acceptable IC configuration by JTAG

  14. 100,000 cycles test 0 error (with 100m optical cable) Result (Readout Part) Maximum L1A trigger rate = 78kHz We can realize that … Optimized module driver, Change to high-speed CPU… for the 100kHz trigger rate.

  15. Conclusion

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