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Beam Test Result of the ATLAS End-cap Muon Level-1 Trigger

Comprehensive test results of the ATLAS End-cap Muon Level-1 Trigger System at CERN SPS. Assessment of functionality, integration, beam profiles, and chamber efficiencies. Detailed analysis of components used and test results for various trigger scenarios.

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Beam Test Result of the ATLAS End-cap Muon Level-1 Trigger

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  1. Beam Test Result of the ATLAS End-cap Muon Level-1 Trigger Chikara Fukunaga Tokyo Metropolitan University On behalf of ATLAS TGC electronics group 9th Workshop on Electronics for LHC Experiment at Amsterdam

  2. Beam Test at CERN SPS H8 • Most of the main (prototype or final) electronicscomponents of ATLAS End-cap Muon Level 1 system have been constructed. • Slice test system worked (LECC2002), and results looked OK • Muon beam of about 100 GeV with 25ns bunched mode was available (May and September 2003) • Confirmation of functionality of the system with chambers and muon • Integration with other ATLAS components 9th Workshop on Electronics for LHC Experiment at Amsterdam

  3. ATLAS End-cap Muon Level 1 Trigger • Thin Gap Chambers (TGC) with wire (r) and strip (f) readout • Level 1 Trigger and 2nd coordinate for MDT muon measurement • Triplet M1Doublet M2 and M3 • Pivot M3 9th Workshop on Electronics for LHC Experiment at Amsterdam

  4. Level 1 Signal Generation Scheme • Dr and Df from the straight line of IP and M3 for each planes • Low-pT with M1 alone or M2 and M3 • High-pT with M1 (triplet) and doublets • R-f coincidence in Sector Logic (SL) 9th Workshop on Electronics for LHC Experiment at Amsterdam

  5. TGC electronics Bunch Xing ID Delay adjustment (Synchronization) Front-end Gate Width 9th Workshop on Electronics for LHC Experiment at Amsterdam

  6. TGC setup at H8 in 2003 9th Workshop on Electronics for LHC Experiment at Amsterdam

  7. TGC electronics at H8 Hi-pT and Star Switch (SSW) On detector part 2 9th Workshop on Electronics for LHC Experiment at Amsterdam TGC Triplet and PS boards (On detector Part 1)

  8. TGC electronics in the H8 hut ROD, Test ROD SL, Control etc. 9th Workshop on Electronics for LHC Experiment at Amsterdam

  9. Electronics components used • Chamber (Triplet 32(Strip) x 24(wire), Doublet both 32 chan.) • ASD board (16ch.) x 2 PS pack • PS board {8 PP ASICs: final design, 2 SLB ASICs: prototype, 1 DCS } x2 • Hi-pT crate • High pT module (4 Hi-pT ASIC: final design) x1 • Star Switch (SSW) module x2 (FPGA based) • HSC • ROD crate(s) • Sector Logic for r-f coincidence (FPGA based) • RODs (ROD and Test-ROD alternatively) (FPGA based) • TTCvi • CCI • Cable • Individually shielded TP Category-5 cable from PS board to Hi-pT crate 10m (ATLAS:15m) for LVDS • Optical fiber from Hi-pT crate to Sector Logic/ROD in the hut 150m (ATLAS:90m) for G-link. 9th Workshop on Electronics for LHC Experiment at Amsterdam

  10. Test results • Chamber efficiency measurements • For finding the best synchronization condition, namely delay constant value set in PP ASIC • For this purpose we have a variable delay (PLL) circuit in PP ASIC in which the delay is adjustable in 25ns/32 precision (every 16 channels) • Trigger efficiency • Low-pT, Hi-pT and r-f coincidence in SL • Validity of readout data • Combined run with MUCTPI for trigger and readout 9th Workshop on Electronics for LHC Experiment at Amsterdam

  11. TGC Chamber efficiencies • PP ASIC parameters • BCID • Delay constant (x-axis) • Gate Width (25,30,35ns) • SLB ASIC • Right, Center and Left bunch data readout Triplet 1st Wire 9th Workshop on Electronics for LHC Experiment at Amsterdam Strip

  12. TGC Trigger efficiency • Gate Width 30ns • Bunch Xing association 100% • 99.7% trigger efficiency • ~3% dead space from chamber supports • ~1% spurious beam trigger • Efficiency of full trigger chain (Low-pT-Hi-pT-Rf) 9th Workshop on Electronics for LHC Experiment at Amsterdam

  13. Beam Profile – Readout check • Readout (SSW and ROD firmware + ROD/ROS software) system worked fine. Minor bug has been identified in SSW FPGA firmware, it was cured quickly. • Beam Profile under the (best) condition of 30ns Gate and 15ns Triplet delay. 9th Workshop on Electronics for LHC Experiment at Amsterdam

  14. Readout/Trigger Validity check with other sub-detector(s) 9th Workshop on Electronics for LHC Experiment at Amsterdam • TGC and MUCTPI process trigger data correctly • Both readout trigger data correctly

  15. Conclusion • We have checked functionality of the TGC Level 1 muon end-cap system with muon beam of 25ns bunched mode at SPS-H8 • Confirmation of validity of design logic of main three ASICs (PP, SLB and Hi-pT) has been done. • System functionality with other sub-detectors and common environment (TTC, DCS) has been also confirmed. 9th Workshop on Electronics for LHC Experiment at Amsterdam

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