Viterbi Decoder: Presentation #4

1. Overall Project Objective: Design of a high speed Viterbi Decoder Stage 4: 9th Feb. 2004 Gate Level Design Viterbi Decoder: Presentation #4 M1 Omar Ahmad Prateek Goenka Saim Qidwai Lingyan Sun Design Manager: Yaping Zhan

2. Status • Design Proposal (finalized) • Architecture Proposal (done) • Final Algorithm Description • Mapping of Algorithm into hardware • High level simulation/emulation in Matlab • Behavioral Verilog simulation and test bench • Gate level Design • Floor Plan • To be done: • Component Layout (10% done) • Chip Layout • Spice Simulation of Entire Chip 18-525, Integrated Circuits Design Project

3. Architecture/Floor Plan Revisions • Small change in our architecture. Instead of using subtractors, comparators are being used. • Floor Plan also to remain unchanged (until we have a better estimate using our component layouts) 18-525, Integrated Circuits Design Project

4. Concerns from last week… • Is an 8 bit ripple carry adder really a better choice than an 8 bit carry look ahead adder ? 18-525, Integrated Circuits Design Project

5. Eight bit ripple carry adder 216 transistors 18-525, Integrated Circuits Design Project

6. Critical Time Analysis of Ripple Carry propagation for 8-bit ripple carry = 1.15 ns 18-525, Integrated Circuits Design Project

7. 4 bit ripple carry look ahead 4 bit schematic of carry look ahead (8-bit has 480 transistors) 18-525, Integrated Circuits Design Project

8. Critical Time Analysis of Carry Look ahead propagation 8-bit carry look ahead = 1.12 ns 18-525, Integrated Circuits Design Project

9. The choice is obvious… 18-525, Integrated Circuits Design Project

10. Original Floorplan 650 BCU Unit ACS Unit Buffering/Routing 350 ML Search TB Unit All units in microns We thought about alternatives to improve ratio 18-525, Integrated Circuits Design Project

11. Floor Plan (alternative ideas) 310 • L shaped BCU Unit BCU Unit ML Search 425 ACS Unit ACS Unit Buffering/Routing TB Unit 18-525, Integrated Circuits Design Project

12. 325 BCU Unit BCU Unit ACS Unit Buffering/Routing ACS Unit ML Search TB Unit Floor Plan (alternative ideas) • Break up 450 18-525, Integrated Circuits Design Project

13. Schematic: top level 18-525, Integrated Circuits Design Project

14. Yes, but we need to go under the hood!! 18-525, Integrated Circuits Design Project

15. Schematic: Top level BCU 18-525, Integrated Circuits Design Project

16. Schematic: BCU cell 18-525, Integrated Circuits Design Project

17. Schematic: ACS unit 18-525, Integrated Circuits Design Project

18. Schematic: ML search 18-525, Integrated Circuits Design Project

19. Schematic: Trace Back Unit 18-525, Integrated Circuits Design Project

20. Verilog Simulation: Top Level 18-525, Integrated Circuits Design Project

21. Critical Path • The critical path lies within the ACS_unit. Adder The delay would be dominated by the adder and the comparator, therefore in worst case the critical path would be the delay of 2 8- bit adders Comparator Approx clock speed = ½*delay = (1/1.15*2) = approx 400 Mhz Mux 18-525, Integrated Circuits Design Project

22. 1-bit adder Layout 18-525, Integrated Circuits Design Project

23. Questions? 18-525, Integrated Circuits Design Project