FPGA-Based Wireless Sensor Network Architecture for High Performance Applications

1. FPGA-Based Wireless Sensor Network Architecture for High Performance Applications J. Valverde Traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power. Nowadays, the complexity and number of tasks of the applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, so most of the times more computing power is required. This extra computing power may be achieved by either more powerful microcontrollers, though more power consumption or, in general, by any solution capable of accelerating task execution. At this point, the use of hardware based systems, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so the overall energy could be reduced. In order to demonstrate this, an innovative WSN node architecture is proposed. Project sponsored by Design Requirements & Features HiReCookie SMART Project • Self-configurable node. • Capability of including different functionalities and changing them remotely at run time. • Digital and analog signal processing. • Cookie platform compliant in functionality and size (60 mm x 40 mm). • Fully testable design. Check points and computer debugging. • System aware of its own power consumption to implement energy saving policies. Power Islands. • Multimedia applications, encryption algorithms, etc. • The design must include hardware and software advantages to provide larger flexibility. RUNNER Project FPGA Virtual architecture HiReCookie & Expansion Board PCB HiReCookie architecture Platform Tests 10,000 Data Blocks FPGA Core Consumption Profile Computing Time Configuration Time Sleep Mode Wake-Up Active SHA1 Encryption Algorithm Theory Results !!!!! 0,52 Configuration Time is Critical 65 % Energy Savings Cookie Node CONCLUSIONS In this work a high performance node architecture for demanding WSN applications based on a commercial SRAM-based FPGA is proposed. FPGA reconfiguration features increase node flexibility, while its hardware nature reduces execution time. Considering the periodic nature of typical WSNs’ tasks, together with power management strategies, high power efficiency is achieved. Experiments have been carried out to validate the node behavior, as well as to quantify the benefits of including hardware components, compared with state-of-the-art low-performance software based solutions.