L16 : Logic Level Design (2)

1. L16 : Logic Level Design (2) 성균관대학교 조 준 동 교수 http://vlsicad.skku.ac.kr

2. Low Power Logic Gate Resynthesis on Mapped Circuit 김현상 조준동 전기전자컴퓨터공학부 성균관대학교

3. Transition Probability • Transition Probability: Prob. Of a transition at the output of a gate, given a change at the inputs • Use signal probabilities • Example: F = X’Y + XY’ • Signal Prob. Of F: Pf = Px(1-Py)+(1-Px)Py • Transistion Prob. Of F = 2Pf(1-Pf) • Assumption of independence of inputs • Use BDDs to compute these • References: Najm’91

4. Technology Mapping • Implementing a Boolean network in terms of gates from a given library • Popular technique: Tree-based mapping • Library gates and circuits decomposed into canonical patterns • Pattern matching and dynamic programming to find the best cover • NP-complete for general DAG circuits • Ref: Keutzer’87, Rudell’89 • Idea: High transition probability points are hidden within gates

5. Example of High Switching Activity Node Internal Mapping in Complex Gate Low Power Cell Mapping

6. Signal Probability vs. Power

7. Spatial Correlation

8. Precomputation logic selectively precompute the output logic values -> reduce switching activity using predictor function Retiming re-positioning the F/F in a pipelined circuit candidates for adding circuit nodes with high hazard activity circuit nodes with high load capacitance g R1 R2 R3 R A CL g g1 NOR CL g2 Logic Synthesis for Low Power y

9. State assignment to minimize the switching activity on high state transition arc can also consider the complexity of the combinational logic experimental result 10% ~17% power reductions Path balancing reduce hazards/glitches key issue in the delay insertion to use the minimum number of delay to achieve the maximum reduction Multi-level network optimization use network don’t care term cost function minimize sum of the number of product terms and the weighted switching activity how changes in the global function of an internal node affects the switching activity of in its transitive fanout experimental result ~10% power reduction Logic Synthesis for Low Power

10. Technology decomposition minimizes the sum of the switching activities at the internal nodes one method to inject high switching activity inputs into the tree as late as possible Technology mapping general principle hide nodes with high switching activity inside the gates H L H Logic Synthesis for Low Power H : high transition node L : low transition node P(a) = 0.3 P(b) = 0.4 a b c P(c) = 0.7 P(d) = 0.5 d a a b b c a d b E(sw) = p(ab)+p(abc) +p(abcd) = 0.246 E(sw) = p(ab)+p(cd) +p(abcd) = 0.512

11. Low Power Logic Synthesis

12. Technology Mapping

13. Tree Decomposition

14. Huffman Algorithm

15. Depth-Constrained Decomposition • Algorithm • problem : minimize SUM from i=1 to m p_t (x_i ) • input : 입력 시그널 확률(p1, p2,íñíñíñ, pn), 높이(h), 말단 노드의 수(n), 게이트당 fanin limit(k) • output : k-ary 트리 topology • Begin • sort (signal probability of p1, p2,íñíñíñ, pn); • while (n!=0) • if (h>logkn) • assign k nodes to level L(=h+1); • /*레벨 L(=h+1)에 노드 k개만큼 할당*/ • h=h-1, n=n-(k-1); /*upward*/ • else if (h<logkn) • assign k nodes to level L(=h+2); • /*이전 레벨 L(=h+2)에 노드 k개만큼 할당*/ • h=h, n=n-(k-1); /*downward*/ • else (h=logkn) • assign the remaining nodes to level L(=h+1); • /*complete; 레벨 L(=h+1)에 나머지 노드를 모두 할당하고 • complete k-ary 트리 구성*/ • for (bottom level L; L>1; L--) • min_edge_weight_matching (nodes in level L); • End

16. Example

17. After Decomposition

18. After Tech. Mapping

19. Precomputation • Power saving • Reduces power dissipation of combinational logic • Reduces internal power to precomputed registers • Opportunity • Can be significant, dependent on; • percentage of time latch precomputation is successful • Cost • Increase area • Impact circuit timing • Increase design complexity • number of bits to precompute • Testability • may generate redundant logic

20. Precomputation Entire function is computed. Smaller function is defined, Enable is precomputed.

21. Precomputation • Before Precomputation Diagram

22. Precomputation • After Precomputation Diagram

23. Precomputation • Before Precomputation - Report

24. Precomputation • After Precomputation - Report

25. Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Entity before_precomputation is port ( a,b : in std_logic_vector(7 downto 0); CLK: in std_logic; D_out: out std_logic); end before_precomputation; Architecture Behav of before_precomputation is signal a_in, b_in : std_logic_vector(7 downto 0); signal comp : std_logic; Begin process (a,b,CLK) Begin if (CLK = '1' and CLK'event) then a_in <= a; b_in<= b; end if; if (a_in > b_in) then comp <= '1'; else comp <= '0'; end if; if (CLK'event and CLK='1') then D_out <= comp; end if; end process; end Behav; Precomputation Example - Before Code

26. Library IEEE; Use IEEE.STD_LOGIC_1164.ALL; Entity after_precomputation is port (a, b : in std_logic_vector(7 downto 0); CLK: in std_logic; D_out: out std_logic); end after_precomputation; Architecture Behav of after_precomputation is signal a_in, b_in : std_logic_vector(7 downto 0); signal pcom, pcom_D : std_logic; signal CLK_en, comp : std_logic; Begin process(a,b,CLK) Begin if (CLK='1' and CLK'event) then a_in(7) <= a(7); b_in(7) <= b(7); end if; pcom <= a xor b; if (CLK='0') then pcom_D <= pcom; end if; CLK_en <= pcom_D and CLK; Precomputation Example - After Code

27. if (CLK_en='1' and CLK_en'event) then a_in(6 downto 0) <= a(6 downto 0); b_in(6 downto 0) <= b(6 downto 0); end if; if (a_in > b_in) then comp <= '1'; else comp <= '0'; end if; if (CLK='1' and CLK'event) then D_out <= comp; end if; end process; end Behav; Precomputation - Example After Code