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Handling Complexities in Modern Large-Scale Mixed-Size Placement

Handling Complexities in Modern Large-Scale Mixed-Size Placement. Jackey Z. Yan Natarajan Viswanathan Chris Chu. Dept. of Electrical & Computer Engineering Iowa State University, Ames, IA 50010. Mixed-Size Placement. Millions of standard cells

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Handling Complexities in Modern Large-Scale Mixed-Size Placement

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  1. Handling Complexities in Modern Large-Scale Mixed-Size Placement Jackey Z. Yan Natarajan Viswanathan Chris Chu Dept. of Electrical & Computer Engineering Iowa State University, Ames, IA 50010

  2. Mixed-Size Placement • Millions of standard cells • Hundreds of macros, e.g., IP cores or memory blocks • All objects are movable with hundreds of fixed I/O objects

  3. Previous Work: Two-Stage Approach • First fix macros, then place standard cells Stage 1 Stage 2 Initial Placement Macro Placer / Legalizer Standard-cell Placer • Capo+Parquet+Capo [S. N. Adya et al., ISPD 2002] • XDP [J. Cong et al., ASP-DAC 2006] • MP-trees based macro placer [T.-C. Chen et al., DAC 2007] • TCG based macro placer [H.-C. Chen et al., ICCAD 2008] • Macro positions are fixed based on an initial placement, which • is generated using some inaccurate WL model • contains many overlaps among the objects • Standard cell positions in initial placement are discarded

  4. Previous Work: Simultaneous Approach • Simultaneous placement of macros and standard cells • Dragon[T. Taghavi et al., ISPD 2006] • Capo Floorplacement [J. A. Roy et al., ISPD 2006] • FastPlace3[N. Viswanathan et al., ASPDAC 2007] • APlace[A. B. Kahng et al., ISPD 2006] • mPL6[T. Chan et al., ISPD 2006] • Kraftwerk[P. Spindler et al., ICCAD 2006] • NTUplace3[T.-C. Chen et al., ICCAD 2006] State of the art: Analytical Placers • Wirelength is approximated (e.g., log-sum-exp, quadratic) • Many overlaps among the objects  Legalization is very hard • Scalability is an issue • Cannot optimize the macro orientations

  5. FLOP: Floorplan-Guided Placer • Effectively integrate the floorplanning and incremental placement algorithms • Efficiently handle large-scale mixed-size designs with all movable objects and fixed I/O objects • Derived Modern Mixed-Size (MMS) placement benchmarks from ISPD05/06 placement benchmarks • Experimental results • State-of-the-art mixed-size placers (simultaneous approach) • Leading macro placers (two-stage approach) Best Wirelength

  6. Cut down problem size • Optimize positions of small objects New Algorithm Flow Block Formation • Direct HPWL minimization • Precise object distribution Floorplanning for overlap-free layout • Optimize macro orientation Wirelength-driven Shifting • Optimize HPWL by shifting • blocks at floorplan level Final positions of big macros Initial positions of small objects Incremental Placement

  7. Advantages of New Algorithm Flow Block Formation • Compared with analytical placer: • Exact HPWL minimization (Steps 1-3) • More precise object distribution (Step 2) • Better scalability (Step 1) • Capability of handling constraints (Step 2) • Avoid legalization of big macros (Step 2) Floorplanning Wirelength-driven Shifting • Compared with two-stage approach: • Do not rely on low-quality initial placement • Respect positions of small objects provided by previous step Incremental Placement

  8. Fixed- outline region Background: Fixed-outline Floorplanning DeFer [Yan et al. DAC 2008] 500 1. Partitioning 240 260 2. Combining 120 140 128 112 3. Back-Tracing 4. Swapping 5 8 7 9 10 9

  9. Original Circuit Block Formation • Integrated into partitioning step of DeFer • Recursively cut the original circuit • By hMetis2.0 • Stopping Criteria: Area% of a subcircuit ≤ 0.15% OR # of objects ≤ 10

  10. Shape Curve Generation for Blocks H H H A’ A A A A W W W Un-rotatable Hard Block Rotatable Hard Block Soft Block

  11. Exact Net Model in Min-Cut Placement Traditional min-cut placement minimizes the wirelength by minimizing the cut value (# of interconnections) Circuit M N Placement Region Cut Nets Longer Nets Exact Net Model Min Cut Min Wirelength ≈ = [Chen et al. ICCAD 2005]

  12. A B V A B A B H B A A B V-cut H-cut B A B A Usage of Net Model in FLOP and H/V H/V H/V βLevels(β= 3 by default) H/V H/V H/V H/V Better Cut ? or

  13. Cut Value Comparison in Net Model Net Bounding Box H W

  14. After Before Wirelength-driven Shifting • Floorplan provides good initial positions for blocks • WL can be further improved by shifting blocks • Formulated optimally as a Linear Programming (LP) problem • Solved by QSopt • Hard block positions are fixed after this step • Soft block positions determine initial small objects positions for following incremental placer

  15. Incremental Analytical Placement Similar to FastPlace3 [Viswanathan et al., ASPDAC 2007] All Objects Positions Physical & Netlist based clustering Coarse global placement Refinement of fine-grain clusters Refinement of flat netlist Legalization and detailed placement Final Placement

  16. Modern Mixed-Size (MMS) Benchmarks • 16 mixed-size placement benchmarks • Derived from ISPD 05/06 Placement Benchmarks • Recover the complexities of modern mixed-size designs • One main change has been made on the original circuits • Macros are freed from the original positions • Publicly available at http://www.public.iastate.edu/~zijunyan

  17. Statistics of MMS Benchmarks

  18. Comparing MMS & Original Benchmarks (* results are cited from RQL paper [DAC 2007])

  19. Experimental Setup • All experiments run on AMD Opteron 2.6 GHz CPU and 8 GB memory • Four groups of experiments: • Comparing FLOP with state-of-the-art mixed-size placers (simultaneous approach) on MMS Benchmarks • HPWL on ISPD05 circuits • Scaled HPWL on ISPD06 circuits • Comparing FLOP with leading macro placers (two-stage approach) on modified ISPD06 circuits • Comparing FLOP with and without macro rotation • Comparing FLOP with and without incremental placement

  20. HPWL Results on MMS Benchmarks Binaries are best-available versions on MMS Benchmarks

  21. Norm HPWL 1.44 1.26 1.08 1.02 1 Normalized Results (Runtime & HPWL)

  22. Results of Non-Rotatable FLOP

  23. Results of Non-Incremental FLOP

  24. HPWL Comparison with Macro Placers The benchmarks are modified ISPD06 circuits (All area I/O pads are made movable. Only newblue1 has fixed I/O pads) [Chen et al. 2008 ICCAD].

  25. HPWL Improvement by Moving Macros Best HPWL: 210.96 (RQL) HPWL:175.99 (FLOP) 19.9% longer

  26. HPWL Improvement by Moving Macros Best Scaled HPWL: 432.58 (NTUplace2) Scaled HPWL: 357.83 (FLOP) 20.89% longer

  27. Conclusion • FLOP – a robust, efficient and high-quality mixed-size placement algorithm • FLOP achieves the best wirelength among all state-of-the-art mixed-size placers and leading macro placers

  28. Runtime Breakdown Partitioning Fixed-Outline Floorplanning Shape Curve Combining Swapping LP-based Shifting Global Placement Incremental Placement Detailed Placement

  29. Future Work • Propose a better stand-alone clustering/block-formation technique • Develop a faster shifting technique to substitute LP-based shifting • Extend current technique to handle fixed macros • Try other floorplanning and incremental placement engines

  30. Thank you!

  31. L L L ( I ) ( II ) ( III ) b l r Exact Net Model Assumption 1: Movable pins are placed at region centers Assumption 2: HPWL is used to measure wirelength

  32. H H H r l m Three Hyperedges in Net Model

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