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More Examples Dataflow/Behavioral Modeling . Section 4.12. Schedule. Homework . Hw2, hw2 & labs have been graded. Preview the lecture materials before the lab. Verilog Modeling. Verilog Modeling Styles Gate-Level Modeling Dataflow Modeling Behavioral Modeling. Data Flow Modeling.
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More Examples Dataflow/Behavioral Modeling Section 4.12
Homework • Hw2, hw2 & labs have been graded. • Preview the lecture materials before the lab.
Verilog Modeling • Verilog Modeling Styles • Gate-Level Modeling • Dataflow Modeling • Behavioral Modeling
Data Flow Modeling Data flow modeling of a combinational logic uses a number of operators that act on operands to produce desired results. The keyword assign is used frequently in the dataflow modeling.
Behavior Modeling • Behavioral modeling represents the digital circuits at a functional and algorithmic level. It is used mostly to describe sequential circuits, but can also be used to describe combinational circuits. • Behavioral description use the keyword always. The event control expression • Specifies when the statements will execute. • The target output statement must be of reg data type.
Verilog HDL Operators A and B are both 4-bit binary numbers. A_gt_B is a logic 1 if A is greater than B. A_lt_B is a logic 1 if A is less than B. A_eq_B is a logic 1 if A is equal to B. A==B is not the same as A=B.
Partial Test Bench for mag_compare.v Use concatenation to form a 4-bit array called B.
Four-Bit Adder Example {C4,S0, S1, S2, S3)=5-bit binary number {A0, A1, A2, A3)=4-bit binary number {B0, B1, B2, B3)=4-bit binary number C0 is a 1-bit binary number
8-to-1 Mux if and else example
