Virtex II-Pro Dynamical Test Application Part A - -

1. Virtex II-Pro Dynamical Test ApplicationPart A -- Performed By: Khaskin Luba Einhorn Raziel Instructor: Rivkin Ina Spring 2004

2. Quick Overview • Examining possible space-compatibility of civilian devices, in order to integrate them in satellites. • Statistically modelingthe device’s robustness to temporary damage and it’s ability to recover in a case of an error. • Testing the device under real-time radiation.

3. The System FPGA Device (Vitex II-Pro)

4. Host GUI Xilinx Tools Hyper Terminal JTAG Port USB Port DUT Virtex II-Pro Evaluation Board (platform) Logic Power PC System Block Diagram

5. Host DUT JTAG Port P130 Module DLP-USB245M Module Virtex II-Pro RIO Ports DIP Switches LCD Leds , Push-Buttons DUT –Device Under Test – Virtex II-Pro Evaluation Board

6. Host DUT The Virtex II-Pro – Closer look • Specifications: • Configurable logic block (CLB) • 18Kb Block-RAMs • 44 18X18 bit multipliers • 4 2.5 Gbps Rocket I/O transceivers • 4 Digital Clock Manager units (DCM) • Power-PC 4.05 CPU

7. Host DUT Graphical User Interface • User transparent • Initializing the testing system • Choosing and loading the testing function • Receiving data via USB and calculating statistical results • GUI was created in C++ language, using Visual Studio 6 • Uses supplied Dynamic Library files (Dll files) In order to control the USB module

8. Host DUT Writing appropriate impl. file Opening USB port Sending start signal Gathering test info Test type decision START End Test condition Opening Excel Closing USB port Delete temporary var. Listening to USB Collecting data to Excel file Test Ended Test in Process Graphical User Interface - Algorithm

9. Host DUT GUI – Main Window Test Type Tests List Status Window

10. Host DUT GUI – Settings Window Programs’ location USB connection & drivers check button

11. Host DUT DLP-USB245M - Features • Fast connection – up to 1 Mb/sec. • Small implementation • Simple Interface • Mounted on a P130 expansion module

12. The Testing Concept

13. The Testing System Flow Creating input and comparison vectors; Updating control signals Loading bit file Waiting for outputs Sending input vectors to MUT Checking outputs; Sending results Single/ Multiple tests? Listening to Host Multiple tests End Test Command Single test Test Ended

14. MCT USB Contr. MUT MUT - Module Under Test The examined modules: • I/O Blocks • Fast Multipliers • Rocket I/O • Digital Clock Manager (DCM) • CLB Memory • CLB Flop-flops • CLB logic • BRAMs • Power-PC

15. MCT USB Contr. MUT USB Controller • Controls reading and writing cycles. • Determines USB’s control signals during reading and writing cycles. • Sets up the relevant data to be sent back to host. • Designed with minimal usage of logic and memory elements.

16. MCT USB Contr. MUT USB Controller

17. MCT USB Contr. MUT MCT • Identical basic structure for all the testing functions: - Defines input and comparison vectors in order to test module’s functionality. - Computes the statistical number of errors and instructs their transference using the USB Controller. • Designed with the ambition to maximize the test’s mapping of each examined module. • Minimal usage of logic and memory elements.

18. MCT USB Contr. MUT MCT USB Controller MUT Example – Fast Multipliers

19. MCT USB Contr. MUT Example – Fast Multipliers • Several blocks of fast multipliers are chained together to achieve 100% mapping. • The input vectors, set by the MCT, diffuse through the multipliers chain. The outputs are being compared with the expected result vectors using several feedbacks. • The calculated errors are being sent via USB, using the USB Controller, in steady time intervals.

20. Design Tools • HDL Designer – Creating hardware applications • MODELSIM – VHDL simulation • Synplify – Synthesis tool • Xilinx ISE Project Navigator – Place and Route • Visual C++ – Designing the GUI

21. Part B - Schedule • Implementing tests for the remainder modules • Learning about PPC & Rocket I/O • Learning EDK, Architecture Wizard • Implementing Power-PC tests • Implementing Rocket I/O tests • Implementing Special logic tests (e.g. one loop tests, various user-controllable tests, etc.) • Redesigning the GUI application respectively.

22. Summary and conclusions • First part goals – complete system framework, including test implementation, USB connection and application design – have been successfully achieved • The initially planned communication channel has been changed from Serial port (UART) to USB port