ESD Evaluation of the Emerging MuGFET Technology

1. ESD Evaluation of the Emerging MuGFET Technology C. Russ et. al 2005 ESD/EOS Conference

2. Slide 2 Oh No! Is ESD Going to be MuGGed by Yet Another Technology Development??

3. Slide 3 Purpose of this work Introduce the exciting new Multi-Gate Advanced Transistor Technology called the �MuGFET� and assess its sensitivity to high current ESD behavior Investigate suitable ESD protection methods for this new technology

4. Slide 4 Outline Introduction: MultiGate FETs (MuGFETs) ESD Characterization Fully depleted (FD) MuGFETs Partially depleted (PD) planar FETs Diodes Failure analysis Protection approaches Conclusions

5. Slide 5 Introduction (1) Classical FET in Bulk Si

6. Slide 6 Introduction (2) Planar FET Device in SOI

7. Slide 7 Introduction (3) MuGFET Device (or �Fin�-FET)

8. Slide 8 Introduction (4)

9. Slide 9 Outline Introduction: MultiGate FETs (MuGFETs) ESD Characterization Fully depleted (FD) MuGFETs Partially depleted (PD) planar FETs Diodes Failure analysis Protection approaches Conclusions

10. Slide 10 Test structures

11. Slide 11 Test structures NMOS and Gate diodes available as MuGFET (�Fin�) and planar SOI types Fin width = 50nm, Fin heights = 88 and 60nm Nickel silicided (no silicide blocking)

12. Slide 12 MuGFET: Grounded Gate NMOS Unprecedented high ESD sensitivity ? failure instantaneous after breakdown! L pushes out breakdown, but no snapback visible

13. Slide 13 MuGFET: MOS-diode, Gate tied high

14. Slide 14 Planar PD SOI NFET: Grounded Gate

15. Slide 15 Gated Diodes: Fins + Planar (fwd. mode)

16. Slide 16 Gated Diodes: Fins + Planar (rev. mode)

17. Slide 17 Outline Introduction: MultiGate FETs (MuGFETs) ESD Characterization Fully depleted (FD) MuGFETs Partially depleted (PD) planar FETs Diodes Failure analysis Protection approaches Conclusions

18. Slide 18 Failure Analysis: NFETs

19. Slide 19 Failure Analysis: Diodes (fwd. mode)

20. Slide 20 Failure Analysis: Pulse Width vs. It2

21. Slide 21 Protection Approaches

22. Slide 22 Conclusions New issues for emerging Multigate technologies: FinFET MOS: extremely ESD-susceptible Local burn-out of fins Planar MOS: reasonable ESD hardness Uniform failure signature (even fully silicided!) Available in same process Lower trigger than FinFET ? local clamp Gate-biased MOS: Possible as protection, BJT conduction must strictly be avoided Gated diodes (Fin-type and planar): Diodes needed in any protection scheme FinFET diodes: high ESD currents possible!

23. Gate Dielectric Integrity along the Road Map of CMOS Scaling including Multi-Gate FET, TiN Metal Gate, and HfSiON High-k Gate Dielectric

24. Slide 24 Investigate: Influences of multi-gate architecture and metal gate on gate dielectric reliability. Demonstrate: Dielectric reliability trend along the road map towards a CMOS process using triple gate architecture, metal gate, and HfSiON gate dielectric. Purpose

25. Slide 25

26. Slide 26

27. Slide 27

28. Slide 28

29. Slide 29

30. Slide 30

31. Slide 31 State of the art gate dielectric reliability can be achieved for CMOS processes using vertical multi-gate architectures. GOX reliability trend along the road map of CMOS scaling will be dominated by metal gates and high-k dielectrics. The use of metal gate increases gate leakage current density and reduces SiO2 reliability margin for PFET devices compared to poly-Si/SiO2. NFET & HfSiON: the extrapolation of dielectric reliability to use conditions needs to consider the strong dependence of gate leakage on gate voltage. PFET & HfSiON: the dielectric reliability meets the level of a standard poly-Si/SiO2 gate stack of same EOT. Conclusions