Design and implementation of a motion coprocessor for the MERITE beacon

1. Design and implementation of a motion coprocessor for the MERITE beacon D.Faura, O.Romain, K. Hachicha and P.Garda SYEL group Laboratoire des Instruments et Systèmes d’Ile de France, LISIF Université Pierre et Marie Curie FRANCE

2. Out line • Introduction • The goal • Architecture of the beacon • Implementation • Experimental Results • Conclusion

3. 1. Introduction • Recent progress in the fields of : • Processing architecture • Electronic implementation • SoC, SIP, … • Wireless telecommunication • Bluetooth, Wifi, Home RF, … • Ad Hoc networks Design of new generation of autonomous Systems

4. Propagation of the alarm Accident Application domains • Military and safety • Monitor the enemies • Robot rescue • Environment • Detection of forest fires • Transport • To avoid car crash Require the design of intelligent network sensors

5. 2. Goal • To propose and model a new architecture of an intelligent wireless beacon for sensor networks applications • To detect and transmit an alarm • To distinguish between a false and a true alarm • To design an electronic implementation • To test and verify the behaviour of the beacon in a real conditions • To integrate • To make an AMS System-On-Chip (RFVSoC Project)

6. 3. Architecture The architecture of the beacon that we propose is composed essentially of 3 units :

7. 3.1 Sensor Unit • Environmental analog sensors • Video chain detection • To give information on the scene • CCD or CMOS cameras

8. 3.1 Sensor Unit • Camera CA88 1/4” With Digital Output • Low power consumption (<100mW). • Data format -YCrCb 4:2:2, GRB 4:2:2, RGB • I2C interface

9. 3.2 Processing Unit • Flexible and upgradeable architecture • FPGA composed by a collection of IP of each functional block • Processor IP to manage different tasks • Data acquisition and transmission • Dedicated IPs for image processing • Motion detection for triggered alarm • Video compression

10. Future binary difference frame Current binary difference frame rf r r r Past binary difference frame s r r rp r r r 3.2.1 Alarm detection • Environmental Sensor • A simple threshold predefined • Camera • A spatio temporal Markov Detector

11. R Produit Codeur Détection Id(t) I(t) Carte binaire de mouvement VAR ICM Buffer O(t) Buffer I(t+1) F S O(t+1) bin Détection Abs P R Buffer 3.2.2 Algorithme principle

12. Future binary difference frame Current binary difference frame rf r r r 0 0 0 0 Past binary difference frame s r r 1 1 rp r r r 0 0 1 0 3.2.3 ICM principle 0 1

13. 3.2.4 Example of results Created binary motion map

14. 3.2.5 Video compression • Used to reduce data rate for the transmission of video signals • 2 encoders studied at present: • Motion Markov JPEG2000 • Standard MPEG4 MMJPEG200 MPEG4 Send bitstream via wireless module

15. 4. Implementation • Experimental prototype designed around a HW/SW platform • Co-Design Used • Altera Nios tool kit • Based on a FPGA (Cyclone EP1C20 Altera) • Architecture: interconnection of different IPs • Acquisition and Wireless Units are plugged Required Hardware and Software Development

16. 4.1 Hw dev : Sensor unit Integrates 3 environmental sensors • Digital Thermo resistive sensor,DS1821 • Gives 8-bit information on environmental temperature with [-55,125°C] range • Analog Magneto Resistive sensor, HMC1002 • To make electronic compass and detect possible ferromagnetic objects close to the beacon • Analog Atmospheric Pressure sensor, MPX2100AP (Motorola) • Analog measures converted by an ADC, AD7810 • 10-bit, 100kSPS

17. 4.2 Hw dev : Wireless unit • Why Bluetooth module ? • Ad hoc network easy to make • Piconet and scatternet patterns • Data rate up to 780 kbit/s • Enough • RfSolution Module BRM01 • SPI interface • Up to 480kbit/s • 115kbit/s measured

18. 4.3 HW dev : Video detection Camera Interface IP Avalon Bus Avalon Bus Markov IP SDRAM DMA Nios Image of the Motion detection stored in the memory

19. 4.4 HW dev : Sensor unit • Camera/Avalon interface realized in Vhdl • Results : YUV signals

20. 4.5 Design of Markov IP memory Binarization Energy comparison model energy difference Data energy Variance

21. 4.6 Results Logic element partition Memory bit partition DSP block elements repartition

22. SOPC BuilderGUI Configure Processor Select & Configure Peripherals, IP Generate Nios IP Processor 4.7 HW dev : Processing Unit Hardware Configuration File HDL source files Synthesis &Fitter Markov IP I2C IP Controller Altera PLD Quartus II APEX 20K

23. 4.8 SW development SOPC Builder GUI Initialization Configure Processor Select & Configure Peripherals, IP Acquisition Generate Nios IP Processor Processing • User Code Compression • C Header files • Custom Library • Peripheral Drivers Compiler, Linker, Debugger Transmission Executable Code GNUPro Tools Altera PLD

24. Spatial Temporel PSNR 4.9 MPEG4 Coder Overview Basic MPEG4 coder Intra Tools Inter Scalabiliy error resilience Reduced resolution sprite Object shape background

25. 4.10 Performances.

26. 5. Experimental Results • Communication with a distant PC realized with an hyper terminal windows application • Communication features : • 20 meters in indoor • 115kbit/s limited by RS232 driver • Visual C++ interface has been developed to display data transmitted

27. 5.1 Experimental Results

28. 6. Conclusion we have introduced • the architecture of an intelligent beacon for wireless sensor networks • first implementation : MERITE with following features • Markov (HW) detector • MPEG4 (SW) compressor • Wireless compression

29. The End Thanks you for your attention