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EE 616 Computer Aided Analysis of Electronic Networks Lecture 2

Learn network scaling, Thevenin/Norton Analysis, Formulation of Circuit Equations, and more in this lecture. Understand KVL, KCL, and apply Sparse Tableau Analysis and Nodal Analysis. Explore modeling and ideal two-terminal elements.

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EE 616 Computer Aided Analysis of Electronic Networks Lecture 2

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  1. EE 616 Computer Aided Analysis of Electronic NetworksLecture 2 Instructor: Dr. J. A. Starzyk, Professor School of EECS Ohio University Athens, OH, 45701 09/09/2005 EE 616

  2. Review and Outline • Review of the previous lecture • -- Class organization • -- CAD overview • Outline of this lecture • * Review of network scaling • * Review of Thevenin/Norton Analysis • * Formulation of Circuit Equations • -- KCL, KVL, branch equations • -- Sparse Tableau Analysis (STA) • -- Nodal analysis • -- Modified nodal analysis EE 616

  3. Network scaling EE 616

  4. Network scaling (cont’d) EE 616

  5. Network scaling (cont’d) EE 616

  6. Review of the Thevenin/Norton Analysis ZTh + – Voc Isc ZTh Thevenin equivalent circuit Norton equivalent circuit Note: attention to the voltage and current direction EE 616

  7. Review of the Thevenin/Norton Analysis 1. Pick a good breaking point in the circuit (cannot split a dependent source and its control variable). 2.Replace the load by either an open circuit and calculate the voltage E across the terminals A-A’, or a short circuit A-A’ and calculate the current J flowing into the short circuit. E will be the value of the source of the Thevenin equivalent and J that of the Norton equivalent. 3. To obtain the equivalent source resistance, short-circuit all independent voltage sources and open-circuit all independent current sources. Transducers in the network are left unchanged. Apply a unit voltage source (or a unit current source) at the terminals A-A’ and calculate the current I supplied by the voltage source (voltage V across the current source). The Rs = 1/I (Rs = V). EE 616

  8. Modeling EE 616

  9. Formulation of circuit equations (cont’d) EE 616

  10. Ideal two-terminal elements EE 616

  11. Ideal two-terminal elements Topological equations EE 616

  12. KVL and KCL • Determined by the topology of the circuit • Kirchhoff’s Current Law (KCL): The algebraic sum of all the currents leaving any circuit node is zero. • Kirchhoff’s Voltage Law (KVL): Every circuit node has a unique voltage with respect to the reference node. The voltage across a branch eb is equal to the difference between the positive and negative referenced voltages of the nodes on which it is incident EE 616

  13. Formulation of circuit equations (cont’d) • Unknowns • B branch currents (i) • N node voltages (e) • B branch voltages (v) • Equations • KCL: N equations • KVL: B equations • Branch equations: B equations EE 616

  14. Branch equations • Determined by the mathematical model of the electrical behavior of a component • Example: V=R·I • In most of circuit simulators this mathematical model is expressed in terms of ideal elements EE 616

  15. Matrix form of KVL and KCL B equations N equations EE 616

  16. Branch equation Kvv + i = is B equations EE 616

  17. branches 1 2 3 j B n o d e s 1 2 i N (+1, -1, 0) { +1 if node i is terminal + of branch j -1 if node i is terminal - of branch j 0 if node i is not connected to branch j Aij = Node branch incidence matrix • PROPERTIES • A is unimodular • 2 nonzero entries in each column EE 616

  18. Equation Assembly for Linear Circuits • Sparse Table Analysis (STA) • Brayton, Gustavson, Hachtel • Modified Nodal Analysis (MNA) • McCalla, Nagel, Roher, Ruehli, Ho EE 616

  19. Sparse Tableau Analysis (STA) EE 616

  20. Advantages and problems of STA EE 616

  21. Nodal analysis 1. Write KCL A·i=0 (N equations, B unknowns) 2. Use branch equations to relate branch currents to branch voltages i=f(v) (B unknowns  B unknowns) • Use KVL to relate branch voltages to node voltages • v=h(e) (B unknowns  N unknowns) Yne=ins N equations N unknowns Nodal Matrix N = # nodes EE 616

  22. Nodal analysis EE 616

  23. N+ N+ N- N+ N- i Rk N- Nodal analysis – Resistor “Stamp” Spice input format: Rk N+ N- Rkvalue KCL at node N+ KCL at node N- EE 616

  24. N+ NC+ NC+ NC- N+ N- Gkvc N- NC- Nodal analysis – VCCS “Stamp” Spice input format: Gk N+ N- NC+ NC- Gkvalue + vc - KCL at node N+ KCL at node N- EE 616

  25. Nodal analysis- independent current sources “stamp” EE 616

  26. Nodal analysis- by inspection Rules (page 36): The diagonal entries of Y are positive and admittances connected to node j 2. The off-diagonal entries of Y are negative and are given by admittances connected between nodes j and k 3. The jth entry of the right-hand-side vector J is currents from independent sources entering node j EE 616

  27. Example of nodal analysis by inspection: (handout) Example 1 Page 35 ~ 36. Example 2: inspection for networks with VCTs Page 40 ~ 41. EE 616

  28. Nodal analysis (cont’d) EE 616

  29. Modified Nodal Analysis (MNA) EE 616

  30. Modified Nodal Analysis (2) EE 616

  31. Modified Nodal Analysis (3) EE 616

  32. General rules for MNA EE 616

  33. Example 4.4.1(p.143) EE 616

  34. Advantages and problems of MNA EE 616

  35. Analysis of networks with VVT’s & Op Amps EE 616

  36. Example 4.5.2 (p.145) EE 616

  37. Example 4.5.5 (p. 148) EE 616

  38. Example 4.5.5 (cont’d) EE 616

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